PID Governor for Dynamic Processor Performance and Power Optimization

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Solution Overview

Problem

It is challenging to dynamically optimize processor performance and power consumption due to unpredictable thread requests and numerous factors affecting processor performance and power usage, requiring an easily implemented method that does not involve complex analysis.

Innovation Solution

A controlling system utilizing a PID governor that determines the actual processor utilization state and adjusts performance and power by setting target utilization values, calculating proportional, integral, and derivative parameters to generate dynamic adjustment values, which are used to adjust operating frequency, voltage, and core count or memory allocation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If processor performance is increased to handle high thread requests, then processing capability is improved, but power consumption increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic frequency scaling and voltage adjustment based on real-time processor utilization monitoring. The controller continuously adapts processor operating parameters (frequency, voltage) to match actual workload demands, transitioning between high-performance and low-power states dynamically rather than statically

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system employs a closed-loop feedback mechanism where processor utilization metrics are continuously monitored and fed back to the controller. This feedback drives automatic adjustment of performance parameters to maintain optimal operating points, balancing performance needs with power consumption constraints

Inventive Principle:
Principle #23Feedback

2Use of energy by moving object

If processor performance is reduced to save power, then power consumption decreases, but processing capability deteriorates

Engineering Contradiction:
Improvepower consumptionVSAvoidprocessing capability
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The system dynamically adjusts processor operating parameters based on real-time workload assessment. When workload is light, the processor operates at lower frequency and voltage to save power; when workload increases, performance is automatically scaled up to meet demands

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes physical operating parameters (frequency, voltage, core count) of the processor based on monitored utilization states. By adjusting these parameters dynamically, the system optimizes the trade-off between power consumption and processing capability for different workload scenarios

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If complex analysis of processor factors is performed to optimize performance, then optimization accuracy is improved, but system complexity increases

Engineering Contradiction:
Improveoptimization accuracyVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts and focuses on the most critical optimization factor - processor utilization rate - while ignoring less significant factors. This selective approach simplifies the control system while maintaining effective optimization by concentrating monitoring and adjustment efforts on the dominant performance determinant

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10216526B2Controlling method for optimizing a processor and controlling system
Publication Date: 2019.02.26 MEDIATEK INC
  • US10216526B2 patent drawing
  • US10216526B2 patent drawing
  • US10216526B2 patent drawing

AI summary

A controlling method for optimizing a processor is provided. The controlling method includes determining an actual utilization state of the processor in a first period, and adjusting performance and/or power of the processor in a second period by a PID (Proportional Integral Derivative) governor based on the actual utilization state in the first period. The second period is after the first period.