PID Interconnect Structure With Embedded Conductor to Cut Via Stitching
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Solution Overview
Problem
The increasing complexity of integrated circuits (ICs) due to more interconnect levels and devices requires improved interconnect solutions that address resistance, thermal dissipation, and design flexibility while reducing manufacturing complexity.
Innovation Solution
Incorporating an embedded conductor within a photo-imageable dielectric (PID) layer, forming a trench and filling it with a conductor, which is electrically coupled to a metal trace, providing a conductive path with controlled depth and width, thereby enhancing electrical and thermal performance and design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via stitching is used to improve electrical performance and thermal dissipation, then resistance decreases and thermal dissipation improves, but manufacturing complexity increases and usable area decreases
Solution Approach 1:
The invention extracts the conductive function from the traditional via stitching approach and embeds it directly within the PID layer. By forming conductive traces inside the PID layer itself rather than using separate via structures to stitch multiple layers, the patent eliminates the need for complex via stitching while maintaining electrical connectivity and thermal dissipation performance.
Solution Approach 2:
The conductive traces are nested within the PID layer structure. The PID layer serves as both the dielectric matrix and the container for the embedded conductive traces, creating a nested configuration where the conductor is embedded inside the dielectric layer, thereby integrating multiple functions into a single structure.
2Reliability
If via stitching is used to improve electrical performance and thermal dissipation, then resistance decreases and thermal dissipation improves, but usable area decreases
Solution Approach 1:
The invention extracts the conductive function from the traditional via stitching approach and embeds it directly within the PID layer. By forming conductive traces inside the PID layer itself rather than using separate via structures to stitch multiple layers, the patent eliminates the need for complex via stitching while maintaining electrical connectivity and thermal dissipation performance.
3Adaptability or versatility
If more interconnect levels are used to support increased number of devices, then electrical connections improve, but manufacturing complexity increases
Solution Approach 1:
The invention merges the dielectric layer and conductive trace formation into a single integrated process. By forming both the PID layer and the embedded conductive traces simultaneously through a dual-damascene or similar process, the patent reduces the number of separate manufacturing steps compared to traditional multi-layer interconnect approaches, thereby simplifying manufacturing while maintaining electrical connectivity.
Data Source
AI summary
A device includes a substrate that includes a photo-imageable dielectric (PID) layer having a layer surface and multiple sidewalls extending from an opening in the layer surface to define a trench. The substrate also includes a conductive interconnect configured to form at least a portion of a conductive path of the substrate. The conductive interconnect includes an embedded conductor within the trench. The conductive interconnect also includes a metal trace on the layer surface and electrically connected to the embedded conductor.