PID Test Structure Using Covering Dielectric for Higher Sensitivity
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Solution Overview
Problem
In deep submicron integrated circuits, Plasma Induced Damage (PID) occurs due to free charge accumulation on conductor surfaces during high density plasma enhanced deposition and etching, leading to gate oxide layer damage and circuit failures, with existing PID tests being insensitive and inaccurate due to the use of gate oxide layers as test objects.
Innovation Solution
A PID test structure comprising a gate structure, a covering dielectric layer, a metal layer structure, and an extraction electrode, where the covering dielectric layer serves as the test object, allowing for adjustable thickness and higher sensitivity, and the metal and gate layers act as electrode plates without requiring the substrate as an electrode, thus improving test accuracy and timeliness and optimizing substrate utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate oxide layer is used as the test object in PID test, then the test can be performed using existing device structures, but the test sensitivity is low and the test is not timely and accurate enough
Solution Approach 1:
The patent separates the test function from the device gate oxide layer by introducing a dedicated covering dielectric layer as the test object. This segmentation allows the test structure to be independently optimized for sensitivity while the device gate oxide layer maintains its functional requirements.
Solution Approach 2:
The covering dielectric layer serves as a sacrificial test object that can be specifically designed and optimized for PID testing purposes. It acts as a dedicated test target that can be structured to maximize charge collection efficiency without compromising device performance.
2Adaptability or versatility
If the gate oxide layer is used as the test object, then the existing device structure can be utilized, but the gate oxide layer thickness cannot be adjusted randomly and must have certain thickness to ensure electrical characteristic
Solution Approach 1:
The patent divides the dielectric layer functionality into two separate layers: the gate oxide layer that maintains device electrical characteristics with fixed thickness, and the covering dielectric layer that serves as the test object with adjustable thickness optimized for charge collection.
Solution Approach 2:
The patent adds a new dimension to the test structure by introducing the covering dielectric layer on top of the gate structure, creating a vertical stacking arrangement that allows independent optimization of test sensitivity without affecting device gate oxide thickness.
3Ease of operation
If the gate layer and substrate serve as electrode plates for PID test, then the test can be performed, but the active region area of the substrate is occupied and contact resistance is high
Solution Approach 1:
The patent transitions from a planar test configuration using substrate active regions to a vertical stacked configuration where the gate layer and metal layer serve as electrode plates, eliminating the need to occupy substrate active region area.
Solution Approach 2:
The patent creates a dedicated test structure that copies the essential elements needed for PID testing (conductive layers and dielectric layer) in a simplified configuration that does not require substrate active region involvement, thereby reducing contact resistance and occupying less area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed PID test structure enhances sensitivity and accuracy by using a covering dielectric layer as the test object, allowing for adjustable thickness and improved charge capture, and avoids occupying active substrate regions, ensuring timely and precise PID damage monitoring.
Implementation Method 1
the covering dielectric layer has higher ability to capture a free charge, so that the PID test structure may have higher sensitivity
Data Source
AI summary
Provided is a Plasma Induced Damage (PID) test structure and a semiconductor test structure, including: a gate structure, including a gate layer; a covering dielectric layer, located on a surface of the gate layer; a metal layer structure, located on a surface of the covering dielectric layer, the metal layer structure including at least one metal layer; and an extraction electrode, electrically connected with the gate layer via a conductive structure.