Piecewise Linear Clock Modulation for Low-EMI Frequency Synthesis
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Solution Overview
Problem
Conventional spread spectrum clock generators face challenges in minimizing Electromagnetic Interference (EMI) while operating at high clock frequencies, as they introduce jitter that degrades microprocessor performance and require complex circuits, and existing methods like phase inversion are difficult to implement on-chip.
Innovation Solution
A clock generator using piecewise linear modulation, comprising a modulation profile generator, delta-sigma modulator, phase-frequency comparator, charge pump, loop filter, voltage-controlled oscillator, and fractional divider, which outputs a multi-phase clock for precise frequency synthesis and minimizes EMI by employing a Phase-Locked Loop feedback divider.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If spread spectrum clock generators use Phase-Locked Loop or Delay Locked Loop to introduce jitter, then EMI reduction is achieved, but microprocessor performance deteriorates and circuit complexity increases
Solution Approach 1:
The patent segments the modulation profile into multiple linear segments instead of using a single complex nonlinear profile. The modulation profile is divided into N segments, each with linear characteristics, which simplifies the circuit implementation while maintaining the spread spectrum EMI reduction effect. This segmentation allows the system to achieve the desired frequency distribution without requiring complex Phase-Locked Loop or Delay Locked Loop circuits.
Solution Approach 2:
The patent changes the modulation approach from traditional jitter-based Phase-Locked Loop methods to a direct digital synthesis method using piecewise linear modulation profiles. By parameterizing the modulation profile with discrete linear segments and using a numerically controlled oscillator, the system achieves spread spectrum clock generation with reduced circuit complexity and without degrading microprocessor performance.
2Object-affected harmful factors
If conventional spread spectrum clock generators use nonlinear modulation profiles, then EMI reduction is maximized, but implementation on-chip becomes difficult
Solution Approach 1:
The patent divides the nonlinear modulation profile into multiple linear segments that can be easily implemented using digital logic circuits. Each linear segment corresponds to a specific frequency range and can be generated using simple digital counters and frequency synthesizers, making the entire system suitable for on-chip integration while maintaining effective EMI reduction through the overall nonlinear frequency distribution.
Solution Approach 2:
The patent replaces traditional analog nonlinear modulation circuits with a digital implementation using a numerically controlled oscillator and piecewise linear lookup tables. This substitution of digital logic for analog circuits enables precise control of the modulation profile while facilitating compact on-chip implementation, as digital circuits are more amenable to integration and offer better stability and reproducibility.
3Speed
If clock frequency is increased to meet high-speed requirements, then processing speed improves, but rising time control and skew adjustment become difficult
Solution Approach 1:
The patent implements a dynamic frequency synthesis system where the oscillator frequency can be precisely adjusted in real-time based on the piecewise linear modulation profile. This allows the system to maintain optimal rising time characteristics across different frequency ranges by dynamically selecting appropriate modulation segments, thereby enabling high clock frequencies while retaining control over signal characteristics.
Solution Approach 2:
The patent incorporates feedback mechanisms through the numerically controlled oscillator that continuously monitors and adjusts the output frequency and phase based on the programmed piecewise linear profile. This feedback control ensures that rising time and skew parameters remain within specified limits even as the clock frequency increases to meet high-speed processing requirements.
Data Source
AI summary
An apparatus and method for generating a clock using piecewise linear modulation are provided. The apparatus includes: a modulation profile generator for outputting an M-bit digital profile obtained by quantizing a piecewise linear modulation profile consisting of two or more linear signals; a delta-sigma modulator for receiving the M-bit digital profile and outputting a K-bit profile obtained by delta-sigma modulating the M-bit digital profile, K being a smaller number than M; a phase-frequency comparator for outputting up and down pulses having the same phase difference as that between a reference clock and a feedback clock; a charge pump for outputting a predetermined current for a time corresponding to the phase difference between the up and down pulses; a loop filter for outputting a control voltage corresponding to the predetermined current; a voltage controlled oscillator (VCO) for outputting a multi-phase clock having a frequency corresponding to a level of the control voltage; and a fractional divider for receiving the multi-phase clock of the VCO, selecting a divider according to the K-bit profile, and outputting a divided clock as the feedback clock. Therefore, it is possible to minimize electromagnetic interference (EMI) using piecewise linear modulation, and to readily implement the apparatus and method on a chip due to the modulation profile consisting of two or more linear signals. In addition, the delicate fractional divider using a multi-phase clock of the VCO and a phase interpolator allows precise frequency interpolation. Furthermore, unnecessary power consumption can be reduced by preventing application of a clock to an unused block.