Piecewise-Slope Superblocks for Fine-Grained NAND Address Mapping
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Solution Overview
Problem
Current memory technologies face challenges in addressing fine-grained resolution issues with NAND-type memory devices, leading to inefficiencies in operations like logical-to-physical address translation, garbage collection, and bad block management, which impact performance and resource management.
Innovation Solution
The formation of superblocks based on piecewise slopes across multiple memory device planes, using a plurality of linear slopes to enhance uniformity in bad block distribution and improve data management efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional address translation methods are used in NAND-type memory devices, then the implementation is simpler, but fine-grained resolution issues arise leading to performance inefficiencies
Solution Approach 1:
The patent divides the memory device into multiple planes with different linear slopes, creating segmented superblocks that can be independently managed. This segmentation enables fine-grained address translation by distributing logical-to-physical mappings across multiple planes, thereby improving data management efficiency while maintaining manageable complexity through structured organization.
Solution Approach 2:
The patent introduces a new dimension by using multiple linear slopes across different planes instead of traditional single-plane address translation. This dimensional approach allows simultaneous access to multiple planes with different slope characteristics, enabling finer resolution in address translation and improving overall productivity without proportionally increasing complexity.
2Reliability
If uniform bad block distribution is achieved through piecewise slopes, then reliability improves, but the construction process becomes more complex
Solution Approach 1:
The patent applies different linear slopes to different planes, creating local quality variations that optimize bad block distribution. Each plane can be independently configured with appropriate slope characteristics, allowing tailored optimization for reliability while maintaining overall system manageability through localized rather than global complexity.
Solution Approach 2:
The patent changes the slope parameter across different planes to achieve uniform bad block distribution. By varying this critical parameter locally across planes rather than using a uniform approach, the system improves reliability through better distribution while the parameter-based control keeps the construction process systematically manageable.
3Measurement precision
If multiple linear slopes are used across multiple planes, then fine-grained resolution is achieved, but the address translation process becomes more complex
Solution Approach 1:
The patent segments the address translation process across multiple planes, each handling a portion of the translation with its own linear slope. This segmentation enables fine-grained precision by distributing the translation workload, while each segment remains independently manageable, preventing overall process complexity from becoming unmanageable.
Solution Approach 2:
The patent adds a plane dimension to address translation, using multiple linear slopes across different planes to achieve finer resolution. This dimensional approach allows parallel translation operations with different precision characteristics, improving overall measurement precision while the structured multi-plane architecture keeps the process systematically manageable.
Data Source
AI summary
Various embodiments provide for a superblock comprising blocks of a memory device (e.g., NAND-type memory device) that are determined (e.g., selected) based on piecewise slopes, which can be used as part of a memory system (e.g., memory sub-system). According to some embodiments, an individual superblock of a memory device is formed or structured using individual blocks selected, from across multiple planes of a memory die, based on a plurality of different linear slopes.


