Piezoelectric Strain Modulation for Transistor Leakage Control
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Solution Overview
Problem
Current microelectronic devices with strained channels face limitations in transistor performance due to increased leakage current at small sizes and the use of expensive materials like MoC, which also restricts compatibility with CMOS technology.
Innovation Solution
A microelectronic device incorporating piezoelectric means to induce variable mechanical strain on transistor channels, improving electrical performance by modulating strain type and intensity based on bias states, applicable to both PMOS and NMOS transistors, and compatible with CMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If strained channels are formed using conventional methods (nitride-based layers for NMOS, SiGe-based layers for PMOS), then transistor speed and consumption are improved, but leakage current increases when channels have very small sizes (less than 10 nanometers)
Solution Approach 1:
The invention changes the fundamental mechanism from lattice-mismatch-induced strain to piezoelectric-field-induced strain. By applying voltage to the piezoelectric material, the strain type and intensity can be dynamically adjusted, allowing optimization of carrier mobility while controlling leakage current in nanoscale channels where conventional fixed strain methods fail.
Solution Approach 2:
The invention replaces the mechanical strain application method (using layers with different lattice parameters) with an electric field-based piezoelectric system. This substitution allows for dynamic control of strain through voltage application, enabling independent optimization of speed and leakage current that is not possible with fixed mechanical strain structures.
2Speed
If MoC material is used for transistor channels to improve electrical performances, then speed and consumption ratio is improved, but the device becomes expensive and incompatible with CMOS technology
Solution Approach 1:
The invention replaces expensive MoC material with standard semiconductor materials (such as silicon) that are compatible with existing CMOS manufacturing processes. The performance enhancement is achieved not through expensive channel material but through the piezoelectric strain application mechanism, making the solution cost-effective and industrially manufacturable.
Solution Approach 2:
The piezoelectric means can serve multiple functions: improving NMOS transistor performance through tension strain, improving PMOS transistor performance through compression strain, and potentially reducing leakage current in both types. This universal applicability replaces the need for different strained channel materials for different transistor types, simplifying manufacturing and reducing costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances transistor performance by optimizing strain conditions for improved speed and consumption ratios, reducing leakage current, and enabling integration into DRAM volatile memory devices without the need for expensive materials.
Implementation Method 1
a layer based on a piezoelectric material, the layer based on piezoelectric material being capable of inducing, when biased, a mechanical strain or several different types of mechanical strains
Data Source
AI summary
An improved microelectronic device, and method for making such a microelectronic device. The device includes one or plural transistors and piezoelectric mechanisms, with an arrangement capable of applying a variable mechanical strain on transistor channels.