Self-Aligned Via Patterning in Piezoelectric Sensors
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Solution Overview
Problem
The existing method for forming conductive vias in multi-layered piezoelectric devices is complex, requiring multiple photomasks and etch processes, which increases time and cost.
Innovation Solution
A method that simplifies the fabrication of multi-layered piezoelectric devices by using a self-alignment technique to form conductive vias, reducing the number of photolithography and etch processes needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photomasks and etch processes are used to form conductive vias, then the precision of via formation is improved, but the device complexity and fabrication time increase
Solution Approach 1:
The patent applies preliminary action by forming sacrificial regions and mandrels before the final via formation. The sacrificial regions are created in specific patterns that guide subsequent etching processes, ensuring precise via placement without requiring multiple photomasks. The mandrels are formed preliminary to define via locations, and the sacrificial regions are removed in advance to create clean via openings.
Solution Approach 2:
The patent uses sacrificial regions as intermediary elements that facilitate via formation. These sacrificial regions act as temporary structures that guide the etching process and are subsequently removed. The mandrels serve as intermediary structures that define via locations during fabrication and are removed after via formation, enabling precise via placement without complex photomask alignment.
2Manufacturing precision
If multiple photomasks and etch processes are used to form conductive vias, then the precision of via formation is improved, but the fabrication time increases
Solution Approach 1:
The patent merges multiple functions into fewer process steps. The sacrificial region formation and mandrel formation are combined into a single patterning step that creates both structures simultaneously. The etching process is designed to perform multiple functions: removing sacrificial regions, creating via openings, and defining via locations in one operation, thereby reducing total fabrication time while maintaining precision.
Solution Approach 2:
The patent performs preliminary actions that enable subsequent steps to be completed more quickly. The sacrificial regions and mandrels are formed in advance with precise geometric relationships that pre-determine via locations. This preliminary structuring allows the final etching step to proceed rapidly without requiring multiple iterative photomask alignments, significantly reducing fabrication time.
3Loss of time
If a self-alignment technique is used to form conductive vias, then the fabrication time is reduced, but the manufacturing precision may be compromised
Solution Approach 1:
The patent implements self-service through self-aligned via formation where the sacrificial regions and mandrels automatically define via locations based on their geometric relationships. The etching process self-aligns to the mandrel structures, eliminating the need for external photomask alignment. The sacrificial regions self-define the via patterns through their predetermined geometric arrangement, achieving both speed and precision.
Solution Approach 2:
The patent uses wet chemical etching processes that exploit chemical selectivity and fluid dynamics to achieve precise via formation. The etchant selectively removes sacrificial regions while being guided by the mandrel structures, creating precisely positioned via openings. The chemical etching process naturally self-aligns to the mandrel geometry, maintaining precision without requiring photomask alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and cost of forming piezoelectric devices by using a single photomask and two etching processes to create conductive vias, thereby improving efficiency and reducing fabrication time.
Implementation Method 1
performing a wet etching process according to the masking layer to concurrently expose an upper surface of each conductive layer in the plurality of conductive layers
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip including a piezoelectric membrane overlying a substrate. A plurality of conductive layers is disposed within the piezoelectric membrane. The plurality of conductive layers comprises a first conductive layer over a second conductive layer. The first conductive layer comprises a first electrode and the second conductive layer comprises a second electrode. A first conductive via is disposed in the piezoelectric membrane and contacts the first electrode. A second conductive via is disposed in the piezoelectric membrane and contacts the second electrode. A sidewall of the second conductive via comprises a vertical sidewall segment overlying a slanted sidewall segment.


