Piezoelectric SOI Wafer for Dynamic Strain Control
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Solution Overview
Problem
Existing techniques for creating strained channel regions in field effect transistors, such as strained silicon-on-insulator technology, often result in insufficient strain and are limited to providing only one type of strain, which is suboptimal for complementary metal oxide semiconductor (CMOS) technology that requires both tensile and compressive strains for N-channel and P-channel transistors.
Innovation Solution
A semiconductor-on-insulator wafer with a piezoelectric material in the electrically insulating layer allows for voltage-controlled strain creation in the channel region, using ferroelectric silicon-doped hafnium dioxide or other piezoelectric materials to apply tensile or compressive strain based on the applied voltage, enabling flexible strain management for both N-channel and P-channel transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strained silicon-on-insulator technology is used to create strain in channel regions, then charge carrier mobility is improved, but only one type of strain (tensile or compressive) can be provided, which is insufficient for CMOS technology requiring both strain types
Solution Approach 1:
The patent applies dynamics by making the strain type switchable rather than fixed. The piezoelectric layer allows dynamic switching between tensile and compressive strain states by applying different polarities of voltage, enabling the system to adapt to different transistor types (N-channel and P-channel) as needed.
Solution Approach 2:
The patent changes the electrical parameter (voltage polarity) applied to the piezoelectric layer to switch between different strain types. By varying the voltage polarity, the strain direction in the channel region can be controlled, providing both tensile and compressive strain for different transistor configurations.
2Ease of manufacture
If fixed strain structures are used in channel regions, then manufacturing is simplified, but the ability to optimize performance for both N-channel and P-channel transistors is lost
Solution Approach 1:
The patent implements universality by designing a single piezoelectric layer structure that can serve multiple functions: providing tensile strain for N-channel transistors, providing compressive strain for P-channel transistors, and maintaining electrical insulation. This multi-functional structure eliminates the need for separate strain engineering processes for different transistor types.
Solution Approach 2:
The piezoelectric layer acts as an intermediary between the semiconductor layer and the substrate. It mediates the strain application to the channel region by converting electrical voltage into mechanical strain through the piezoelectric effect, providing a controlled and reversible strain mechanism that simplifies manufacturing while enabling performance optimization.
3Adaptability or versatility
If voltage-controlled piezoelectric strain is applied to channel regions, then both tensile and compressive strain can be provided for optimal CMOS performance, but device complexity increases due to the need for voltage control mechanisms
Solution Approach 1:
The patent merges the strain control function with the existing gate structure by integrating the piezoelectric layer into the semiconductor-on-insulator substrate. The voltage control is combined with the standard transistor fabrication process, using the same electrode structures already present in CMOS devices, thereby minimizing additional complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances charge carrier mobility in the channel region, improving the performance of both N-channel and P-channel transistors by dynamically controlling strain, thereby increasing conductivity and ON-current by up to 40%.
Implementation Method 1
The electrically insulating layer includes a piezoelectric material... the piezoelectric material creates a strain at least in the channel region when a voltage is applied thereto
Data Source
AI summary
A semiconductor-on-insulator wafer includes a support substrate, an electrically insulating layer over the support substrate and a semiconductor layer over the electrically insulating layer. A semiconductor structure includes a transistor. The transistor includes an electrically insulating layer including a piezoelectric material over a support substrate, a semiconductor layer over the electrically insulating layer, a source region, a channel region and a drain region in the semiconductor layer, a gate structure over the channel region, a first electrode and a second electrode. The first electrode and the second electrode are provided at laterally opposite sides of the electrically insulating layer. The first and second electrodes are electrically insulated from the semiconductor layer and configured for applying a voltage to the piezoelectric material of the electrically insulating layer. The piezoelectric material creates a strain at least in the channel region in response to the voltage applied thereto.