Piezoelectric Layer Stress Engineering in Semiconductor Devices
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Solution Overview
Problem
Existing semiconductor devices face challenges in controlling carrier mobility due to non-uniform stress application in channel regions, leading to increased manufacturing costs and potential crystal defects, particularly when trying to apply both compressive and tensile stresses for PMOS and NMOS transistors.
Innovation Solution
A semiconductor device incorporating a piezoelectric layer, such as BaTiO3, is used to cover the gate electrode and spacer, allowing for controlled stress application through an electric field, enabling precise manipulation of compressive stress in the channel region without the need for complex and costly manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If a Si3N4 film is used as a liner insulation film to control stress magnitude by varying thickness, then stress control is achieved, but manufacturing precision deteriorates due to non-uniformity in film thickness deposition
Solution Approach 1:
The patent replaces the mechanical stress control method (varying Si3N4 film thickness) with an electric field-based control method using a piezoelectric layer. The piezoelectric layer generates stress through voltage application, allowing precise stress control without relying on film thickness deposition uniformity. This substitutes a mechanical deposition process with an electrical control mechanism.
Solution Approach 2:
The patent changes the control parameter from physical dimension (film thickness) to electrical parameter (voltage). By applying different voltages to the piezoelectric layer, stress magnitude can be precisely controlled without the manufacturing precision issues associated with thin film deposition. The stress is controlled by electrical parameter adjustment rather than mechanical dimension control.
2Stress or pressure
If different Si3N4 films are formed for PMOS and NMOS transistors to apply compressive and tensile stresses respectively, then desired stress is applied to each transistor type, but device complexity and manufacturing cost increase due to requiring multiple deposition apparatus
Solution Approach 1:
The patent makes the piezoelectric layer universal for both PMOS and NMOS transistors. A single piezoelectric layer deposition process can serve both transistor types, and by controlling the voltage polarity and magnitude, both compressive and tensile stresses can be applied as needed. This eliminates the need for separate Si3N4 film formation processes for different transistor types.
Solution Approach 2:
The patent introduces dynamic control capability where the piezoelectric layer can switch between generating compressive and tensile stresses by changing the applied voltage polarity. This dynamic adaptability allows a single structure to serve multiple stress requirements, replacing the static need for different films for different transistor types.
3Reliability
If a strained Si substrate is used to apply stress to the channel region, then carrier mobility is improved, but reliability deteriorates due to easy occurrence of crystal defects and junction leak
Solution Approach 1:
The patent introduces a piezoelectric layer as an intermediary between the transistor structure and the stress application mechanism. This intermediary layer allows stress to be applied to the channel region without permanently straining the silicon substrate, thereby avoiding crystal defects and junction leaks while still achieving the desired carrier mobility enhancement through controlled stress.
4Stress or pressure
If the number of fabrication steps is increased to successfully fabricate strained Si substrate, then stress application is achieved, but productivity decreases and manufacturing cost increases
Solution Approach 1:
The piezoelectric layer is formed as a preliminary structure that enables stress control without requiring complex subsequent fabrication steps. The stress application capability is built into the device structure early in the fabrication process, eliminating the need for additional elaborate steps required for strained Si substrate fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves controllability and stability of stress application, enhances carrier mobility, reduces manufacturing costs, and allows for precise engineering of stress, thereby improving transistor performance without the limitations of traditional methods.
Implementation Method 1
a piezoelectric layer which is provided to cover the gate electrode and has one end and the other end connected between the first and second contact wiring lines
Data Source
AI summary
A semiconductor device according to an embodiment includes an insulated-gate field-effect transistor including a gate insulation film provided on a major surface of a semiconductor substrate, a gate electrode provided on the gate insulation film, and a source and a drain provided spaced apart in the semiconductor substrate such that the gate electrode is interposed between the source and the drain, a first contact wiring line which is provided on the source, a second contact wiring line which is provided on the drain, and a piezoelectric layer which is provided to cover the gate electrode and has one end and the other end connected between the first and second contact wiring lines.