Piezoresistor Interconnect Layout for Stable Pressure Sensor Output

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Solution Overview

Problem

The stress distribution in a semiconductor substrate changes due to the layout of metal interconnects, affecting the output characteristics of pressure detection signals, and the stress balance film alone cannot sufficiently mitigate this impact, leading to reduced pressure detection accuracy.

Innovation Solution

A pressure detection element with a semiconductor substrate featuring a diaphragm and frame, incorporating a bridge circuit with piezoresistors connected by first metal interconnects and diffusion interconnects, where the first metal interconnects are positioned outside a specific radius from the piezoresistors, and a pressure sensor that includes a flow path and meter to measure pressure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If metal interconnects are laid out to electrically connect piezoresistors, then electrical connectivity is achieved, but stress distribution changes causing output characteristic shifts

Engineering Contradiction:
Improveelectrical connectivityVSAvoidoutput characteristic stability
Core Design Contradiction:
Ease of manufactureVSMeasurement precision

Solution Approach 1:

The patent extracts the metal interconnect from the region near the piezoresistor by defining an exclusion zone (first region) with a specific radius (0.5L1 to L1) around each piezoresistor. The metal interconnect is routed outside this exclusion zone, thereby removing the source of stress-induced measurement errors while preserving electrical connectivity through alternative routing paths.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the interconnection path into two parts: a diffusion interconnect region (within the exclusion zone) and a metal interconnect region (outside the exclusion zone). This segmentation allows the use of diffusion-based connections near the piezoresistor to avoid stress effects, while metal interconnects are used in regions where they do not interfere with piezoresistor stress fields.

Inventive Principle:
Principle #1Segmentation

2Reliability

If stress balance film is applied to mitigate stress, then some stress compensation is achieved, but pressure detection accuracy remains insufficient

Engineering Contradiction:
Improvestress compensationVSAvoidpressure detection accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent introduces a diffusion interconnect as an intermediary between the piezoresistor and the metal interconnect. This diffusion interconnect acts as a mediator that transitions the electrical connection from the stress-sensitive piezoresistor region to the metal interconnect in the stress-free exclusion zone, thereby eliminating the direct stress coupling that limits the effectiveness of stress balance films alone.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Improves pressure detection accuracy by reducing the influence of stress distribution changes on piezoresistors, enhancing signal stability and precision.

Implementation Method 1

a pressure detection element configured to detect a pressure from a fluid based on a change in electrical resistance in a piezoresistor provided in a diaphragm of a semiconductor substrate

Methodology Applied
Scientific EffectPiezoresistive effect: Piezoresistive Effect

Data Source

PatentEP4650737A1Pressure detection element and pressure sensor
Publication Date: 2025.11.19 MITSUMI ELECTRIC CO LTD
  • EP4650737A1 patent drawingFigure 1
  • EP4650737A1 patent drawingFigure 2
  • EP4650737A1 patent drawingFigure 3

AI summary

A pressure detection element includes a semiconductor substrate that includes a diaphragm and a frame enclosing the diaphragm in a plan view; and a bridge circuit that includes a plurality of piezoresistors disposed over the diaphragm, a first metal interconnect configured to electrically connect adjacent piezoresistors of the piezoresistors, and a diffusion interconnect disposed between each of the piezoresistors and the first metal interconnect. The first metal interconnect is disposed in a remaining region excluding a first region in the semiconductor substrate. The first region is a region of a plurality of imaginary circles having a radius of a length that is 0.5 L1 or more and less than L1 from a center of each of the piezoresistors, where L1 denotes a shortest distance between each of the piezoresistors and an outer periphery of the frame in the plan view.