Pillar-Shaped Active Region Bit-Line Insulation

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Solution Overview

Problem

Conventional semiconductor devices fabricated using reduced design rules face structural and functional instability due to electrical insulation issues between cells, often resulting in short circuits in bit-line bridges and gate electrodes.

Innovation Solution

The method involves forming pillar-shaped active regions in semiconductor substrates with a blocking film to selectively expose sidewalls, allowing for the formation of bit-lines on these exposed areas, which includes etching predetermined portions, forming spacers, and using silicide films to improve insulation between cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If reduced design rules are used to increase integration density, then productivity and device miniaturization are improved, but electrical insulation between cells deteriorates leading to short circuits

Engineering Contradiction:

Improveintegration densityVSAvoidelectrical insulation between cells

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The bit-line is repositioned from a planar configuration to a three-dimensional configuration by forming it on the exposed sidewall of the lower portion of the pillar-shaped active region. This vertical placement in the third dimension provides natural electrical insulation between adjacent cells while maintaining high integration density, as the bit-line is physically separated from the gate electrode and other cell components through the pillar structure.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The active region is divided into distinct upper and lower portions with different functions. The upper portion contains the gate electrode and channel, while the lower portion exposes a sidewall for bit-line formation. This segmentation creates physical separation between the bit-line and the main transistor structure, improving electrical insulation between cells while allowing continued use of reduced design rules.

Inventive Principle:

Principle #1Segmentation

2Ease of manufacture

If conventional fabrication methods are used with reduced design rules, then manufacturing cost is reduced, but structural and functional stability deteriorates

Engineering Contradiction:

Improvemanufacturing costVSAvoidstructural and functional stability

Core Design Contradiction:

Ease of manufactureVSStability of the object's composition

Solution Approach 1:

The blocking film is applied selectively only to specific regions of the active region sidewalls, namely the lower portion where the bit-line will be formed. This localized treatment provides enhanced structural definition and functional stability at the critical bit-line interface without requiring changes to the entire device structure, maintaining compatibility with conventional fabrication processes.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The blocking film acts as an intermediary layer between the active region sidewall and the bit-line. It provides a controlled interface that enhances structural stability and defines the electrical boundary, allowing the bit-line to be formed with precise control over its position and electrical isolation, thereby improving overall device stability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances electrical insulation between cells, reducing the likelihood of short circuits and maintaining structural and functional stability even with reduced design rules, thereby improving the overall performance of semiconductor devices.

Implementation Method 1

forming a pillar-shaped active region by etching a portion of a semiconductor substrate

Methodology Applied

Scientific EffectEtching:

Implementation Method 2

forming a bit-line selectively on the exposed sidewall of the lower portion of the pillar-shaped active region

Methodology Applied

Scientific EffectSilicide formation:

Data Source

PatentUS7615817B2Methods of manufacturing semiconductor devices and semiconductor devices manufactured using such a method

Publication Date: 2009.11.10 SAMSUNG ELECTRONICS CO LTD

AI summary

A method of manufacturing a semiconductor device includes forming a pillar-shaped active region by etching a portion of a semiconductor substrate, forming a blocking film selectively exposing a sidewall of a lower portion of the pillar-shaped active region, and forming a bit-line selectively on the exposed sidewall of the lower portion of the pillar-shaped active region.