Pillar Array Layout for Uniform Electrochemical Plating Heights
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Solution Overview
Problem
Conventional electrochemical plating processes for forming pillars in semiconductor die assemblies result in non-uniform pillar heights due to varying lateral densities, leading to unreliable electrical and thermal connections between stacked dies.
Innovation Solution
The use of pillars with different target widths and the strategic placement of dummy pillars to offset the effects of differing lateral densities on metal deposition rates during electrochemical plating, ensuring uniform pillar heights and reliable interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional electrochemical plating is used to form pillars, then the manufacturing process is simple and fast, but the pillar heights become non-uniform due to varying lateral densities
Solution Approach 1:
The patent applies local quality by varying the photoresist pattern density and pillar lateral dimensions in different regions of the wafer. Specifically, regions with higher lateral pillar density use sparser photoresist patterns and smaller pillar dimensions, while regions with lower lateral pillar density use denser photoresist patterns and larger pillar dimensions. This local adjustment of pattern density and pillar size compensates for the non-uniform metal deposition rates caused by varying lateral densities, ensuring uniform pillar heights across the entire wafer while maintaining the efficiency of conventional electrochemical plating.
2Adaptability or versatility
If pillars with varying heights are formed, then the electrochemical plating process accommodates different lateral densities, but the electrical and thermal connections become unreliable
Solution Approach 1:
The patent applies parameter changes by systematically adjusting the photoresist pattern density and pillar lateral dimensions as compensatory parameters. By changing these geometric parameters based on the local lateral pillar density, the process ensures uniform metal deposition and uniform pillar heights, thereby maintaining reliable electrical and thermal connections between stacked semiconductor dies despite variations in overall pillar density across the wafer.
3Ease of manufacture
If larger gaps between pillars and bond pads occur, then the package can be manufactured with varied pillar heights, but the package becomes inoperative or has reduced functionality
Solution Approach 1:
The patent applies preliminary action by pre-compensating for non-uniform metal deposition through carefully designed photoresist patterns and pillar dimensions before the electrochemical plating process begins. This preliminary geometric adjustment ensures that pillars are formed with uniform heights from the outset, preventing excessive gaps between pillars and bond pads, and eliminating the need for post-manufacturing corrections or scrapping of defective packages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces height variations among pillars, enhancing the reliability of electrical and thermal connections by maintaining consistent pillar heights, thus improving the functionality and yield of semiconductor die assemblies.
Implementation Method 1
metal is electrochemically plated onto the unmasked portion of the die surface
Data Source
AI summary
A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.