Semiconductor Pillar Array Assembly for Probeable Interconnects
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Solution Overview
Problem
Existing semiconductor device assemblies face limitations in electrical interconnection and testing capabilities, particularly when connected to external devices, as traditional methods like solder connections may not allow for universal compatibility and do not facilitate easy testing.
Innovation Solution
The implementation of a semiconductor device assembly with a plurality of pillars extending from the bottom surface, formed by filling vias with conductive materials like copper, arranged in a rectangular array, which are electrically connected to pads and interconnects, enabling both efficient electrical connections and testability through exposed pads or coatings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional solder connections are used to interconnect semiconductor devices, then electrical connection is achieved, but compatibility with various devices is limited and testing capability is reduced
Solution Approach 1:
The pillar array configuration provides universal electrical interconnection capability that can connect to different device types (semiconductor devices, substrates, circuit boards) whereas traditional solder balls are limited to specific applications. The pillars serve multiple functions including electrical connection and test access points
Solution Approach 2:
The pillars act as intermediary connection elements between the semiconductor device and external devices or substrates. They provide a standardized interface that mediates between different connection requirements, enabling both universal compatibility and test access through the same structure
2Ease of operation
If solder balls are used for connection, then electrical interconnection is provided, but the connection does not permit testing ability
Solution Approach 1:
The testing capability is extracted as a separate function from the connection function. The pillars provide both connection and test access, allowing probes to contact the pillars for testing while maintaining electrical connection functionality, separating these needs from traditional solder ball limitations
3Difficulty of detecting and measuring
If pillars are exposed for testing, then testability is improved, but the conductive material may be damaged
Solution Approach 1:
The pillars are formed as composite structures with a conductive core material (copper, tungsten, or aluminum) providing electrical conductivity and a protective coating material providing mechanical strength and protection. This composite structure allows the pillars to be contacted by probes for testing while the protective coating prevents damage to the conductive material
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for robust electrical interconnections between semiconductor devices and substrates, enhancing compatibility with various devices and enabling effective testing by allowing probes to contact exposed pillars without damaging the conductive material, thus improving the operational functionality and versatility of semiconductor device assemblies.
Implementation Method 1
The plurality of pillars may be in a rectangular array positioned adjacent to a side of the semiconductor device... formed from vias filled with a conductive material... The vias may be filled with copper, tungsten, poly silicon, or the like
Data Source
AI summary
A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.