3D NAND Pillar Array with Variable Pitch Lithography
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Solution Overview
Problem
In manufacturing three-dimensional vertical channel NAND memory arrays, irregularities in hole patterning lead to imaging errors and increased complexity in photomask fabrication, making it challenging to achieve high-density memory devices with reduced imaging errors.
Innovation Solution
A memory device architecture featuring a stack of conductive layers with pillars arranged in a specific layout pattern, where pillars are series-connected at cross-points, and source lines are disposed vertically through the pillars, with remnants of pillars and conductive plugs separated by insulating spacers to maintain uniform lithography and enhance density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If OPC (optical proximity correction) is used to achieve uniform patterning between center holes and edge holes, then imaging errors are reduced, but the complexity of the photomask and fabrication cost increase
Solution Approach 1:
The patent applies different pitch values for different regions of the memory array. Center holes use a first pitch while edge holes use a second pitch, allowing each region to be optimized independently for its specific imaging characteristics without requiring complex OPC across the entire array.
Solution Approach 2:
The patent changes the geometric parameter (pitch) of the hole array based on location. By varying the pitch between center and edge regions, the patent achieves uniform patterning while avoiding the need for complex photomask OPC techniques.
2Manufacturing precision
If irregularities in hole patterning are addressed using complex photomask OPC, then imaging errors reduce, but fabrication cost increases
Solution Approach 1:
The patent implements location-specific pitch optimization where center holes and edge holes have different pitch values tailored to their respective imaging requirements. This localized approach achieves uniform patterning without requiring expensive OPC photomasks.
Solution Approach 2:
The patent pre-compensates for imaging errors by designing different pitch values in advance for center and edge regions. This preliminary geometric optimization eliminates the need for costly post-manufacturing OPC corrections.
3Ease of manufacture
If edge holes are positioned closer to source lines and center holes are positioned farther away, then manufacturing is simplified, but imaging errors increase due to pattern irregularities
Solution Approach 1:
The patent changes the pitch parameter based on hole location. Center holes use a first pitch value while edge holes use a second pitch value, compensating for the different distances to source lines and achieving uniform patterning across the entire array.
Data Source
AI summary
A memory device comprises a stack of conductive layers, and an array of pillars through the stack. Each of the pillars comprises a plurality of series-connected memory cells located in a layout pattern of pillar locations at cross-points between the pillars and the conductive layers. The pillars in the array are arranged in a set of rows of pillars extending in a first direction. First and second source lines are disposed vertically through the pillars of first and second particular rows of pillars. The set of rows of pillars includes a subset of rows of pillars including multiple members disposed between the first source line and the second source line. A source line conductor is disposed beneath and electrically connected to the first source line, the second source line, and the subset of rows of pillars disposed between the first and second source lines.