Semiconductor Pillar Bit Line Trenches for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices integrate and shrink in size, the data maintenance performance of memory devices worsens due to increased bit line resistance, voltage, current, and parasitic capacitance between adjacent bit lines in traditional MOSFET structures.
Innovation Solution
A semiconductor structure is formed with bit line isolation trenches and gaps at their bottom corners, allowing for the etching of semiconductor pillars to create bit line trenches, where part of the bit line is buried in the trench and another part is buried in the pillar, reducing resistance, voltage, and current while minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional MOSFET structure with planar channel is used, then device integration is simplified, but bit line resistance and parasitic capacitance increase
Solution Approach 1:
The patent transitions from a planar channel structure to a vertical channel structure by forming semiconductor pillars extending in the depth direction. This dimensional change allows the bit line to contact the channel at multiple points along the pillar, reducing resistance and parasitic capacitance while maintaining integration simplicity
Solution Approach 2:
The bit line is divided into multiple segments that contact different portions of the vertical channel at different depths. This segmentation allows current to be distributed across multiple contact points, reducing the overall bit line resistance and parasitic capacitance
2Object-affected harmful factors
If bit line isolation layer completely fills the isolation trench, then isolation is improved, but etching access to bit line trench becomes difficult
Solution Approach 1:
The bit line isolation layer is selectively positioned within the isolation trench, with different regions having different properties. The isolation layer is present in some areas to provide isolation but absent in specific regions to create etching access paths, achieving both isolation and manufacturability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure reduces bit line resistance, voltage, and current, and decreases parasitic capacitance between adjacent bit lines, thereby enhancing the performance of the semiconductor device.
Implementation Method 1
A first semiconductor pillar is etched in the first direction through the gap to form a bit line trench
Data Source
AI summary
A method for forming a semiconductor structure includes: providing a semiconductor substrate including a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals in a first direction; in which the bit line isolation trenches extend in a second direction, the first direction being perpendicular to the second direction; forming a bit line isolation layer in a bit line isolation trench; in which a gap is provided between the bit line isolation layer and the bit line isolation trench, in which the gap is located at a bottom corner of the bit line isolation trench and extends in the second direction, and exposes part of the bottom of the bit line isolation trench; etching a first semiconductor pillar in the first direction through the gap to form a bit line trench; forming a bit line in the bit line trench.