Pillar-shaped bumps with holes for semiconductor packages
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Solution Overview
Problem
As semiconductor packages are scaled down, the reduced distances between bumps increase the probability of electrical shorts and affect the adhesion between bumps, leading to reliability issues in the semiconductor package.
Innovation Solution
The use of pillar-shaped bumps with holes on substrates and semiconductor chips, where the holes are filled with a solder material to enhance bonding strength and minimize solder thickness, thereby reducing electrical bridges and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor packages are scaled down to reduce size, then package dimensions are reduced, but the distance between bumps decreases leading to increased probability of electrical shorts
Solution Approach 1:
The patent extracts the harmful solder material from the sidewalls of bumps by forming holes through the bumps and removing solder from these regions. This extraction eliminates the source of electrical shorts while preserving the bonding function of the bumps, allowing continued package scaling without proportionally increasing short circuit risk
Solution Approach 2:
The patent introduces porous structures (holes) through the bump material, creating a controlled void space that prevents solder accumulation on sidewalls. These holes act as pathways for solder to flow through rather than accumulate, reducing the risk of electrical bridges between adjacent bumps while maintaining structural integrity
2Volume of moving object
If semiconductor packages are scaled down, then package size is reduced, but adhesion between bumps becomes more critical affecting reliability
Solution Approach 1:
The patent applies local quality by concentrating solder material specifically at the bonding interfaces (pad-bump contacts) while removing it from sidewall regions. This localized solder distribution enhances adhesion strength where needed for bonding while eliminating the harmful effect of sidewall solder that could cause electrical shorts
Solution Approach 2:
The patent performs preliminary actions by forming holes through bumps before the bonding process, and selectively filling only certain regions with solder material. This preliminary structuring ensures that solder is positioned optimally for adhesion while preventing its presence in regions that would cause electrical shorts
3Strength
If solder material is formed on sidewalls of bumps, then bonding is facilitated, but electrical bridges between bumps increase
Solution Approach 1:
The patent extracts solder material from the sidewall regions of bumps by forming holes and selectively removing or excluding solder from these areas. This extraction eliminates the harmful electrical bridge formation while preserving sufficient solder at the bonding interfaces to maintain strong adhesion
Solution Approach 2:
The holes formed through the bumps act as intermediaries that guide solder flow and distribution. These hole structures mediate between the need for solder bonding and the need to prevent electrical shorts, allowing solder to occupy only the appropriate regions for bonding while excluding it from harmful sidewall positions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enhances bonding reliability by minimizing solder thickness on sidewalls and preventing electrical shorts, resulting in improved adhesion and uniform solder formation.
Implementation Method 1
the adhesive agent substantially fills the hole of the bump and bonds the conductive electrode pattern to the substantially pillar-shaped bump
Data Source
AI summary
Substrates and semiconductor chips are provided. The substrate or the semiconductor chip includes a body and a substantially pillar-shaped bump disposed on a first surface of the body. The pillar-shaped bump has a hole penetrating a portion thereof. Related semiconductor packages are also provided. Further, related methods are provided.