Pillar Capacitor Alignment via High-Power Etching
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Solution Overview
Problem
As semiconductor devices are scaled down to achieve higher integration and density, the reduction in transistor size and capacitor distance poses challenges in manufacturing efficient pillar type capacitors that provide adequate capacitance while maintaining proper alignment and structural support.
Innovation Solution
A method involving a semiconductor substrate with specific connecting pads and insulating layers, where high-power etching forms vertical holes corresponding to the pads, allowing for the formation of pillar type capacitors with lengths from 1 to 1.8 micrometers, aligned with second connecting pads in a hexagonal lattice arrangement, providing proper capacitance and structural support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size and capacitor distance are reduced to achieve higher integration and density, then device integration and density are improved, but manufacturing precision and alignment of pillar type capacitors deteriorate
Solution Approach 1:
The patent applies preliminary action by forming insulating layers and defining pad structures before etching the vertical holes for pillar capacitors. The insulating layers are deposited and patterned in advance to establish precise alignment references, ensuring that subsequent etching and capacitor formation occur at the correct positions despite reduced feature sizes. This preparatory structuring enables high-density integration while maintaining manufacturing precision.
Solution Approach 2:
The patent utilizes parameter changes by optimizing etching conditions with power in the range of 900-1100 W and air flow rates of 1-3 SCCM to achieve precise vertical hole formation. By carefully controlling these process parameters, the method maintains alignment precision even as transistor and capacitor dimensions are reduced for higher density integration.
2Manufacturing precision
If etching power is increased to form vertical holes with proper depth and alignment, then manufacturing precision is improved, but energy consumption increases
Solution Approach 1:
The patent optimizes etching parameters by specifying power in the range of 900-1100 W and air flow rates of 1-3 SCCM. This parameter optimization achieves the necessary vertical hole precision for pillar capacitor alignment while minimizing energy consumption. The balanced parameter selection avoids excessive power usage while maintaining sufficient etching precision for high-density device fabrication.
3Reliability
If pillar type capacitor length is increased to provide adequate capacitance, then capacitance is improved, but device height and complexity increase
Solution Approach 1:
The patent transitions from planar capacitor structures to vertical pillar-type capacitors, utilizing the vertical dimension to achieve adequate capacitance. By forming capacitors in the depth direction with lengths of 1-1.8 micrometers through vertical hole etching, the design provides sufficient capacitance without increasing lateral device footprint or overall device complexity, enabling high-density integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of semiconductor devices with pillar type capacitors that offer appropriate capacitance and high distribution density, supporting the performance of memory cells in dynamic random access memory (DRAM) devices.
Implementation Method 1
etching the insulating layer and forming a plurality of vertical holes corresponded to the second connecting pads respectively; The power of the etching is from 900 W to 1100 W
Data Source
AI summary
A semiconductor includes a semiconductor substrate and pillar type capacitors. The semiconductor substrate includes first connecting pads and second connecting pads. The second connecting pads are disposed on the first connecting pads respectively, and the pillar type capacitors are disposed on the second connecting pads respectively. A first ends of the pillar type capacitors are connected to the second connecting pads respectively, and a second ends of the pillar type capacitors area at the opposite side of the first ends. The distance between the first end and the second end of each of the pillar type capacitors is from 1 micrometer to 1.8 micrometer. A manufacturing method is also provided.