3D Pillar Capacitor Structure for Higher Density Without Cracking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated chips face challenges in increasing capacitance density while maintaining structural integrity due to limitations in reducing trench pitch, which can lead to cracking and delamination of capacitor structures.
Innovation Solution
The use of conductive pillar structures vertically extending from a conductive base layer, laterally offset from one another, with conductive and dielectric layers wrapping around these pillars, allows for a reduced pillar pitch without compromising structural integrity, thereby increasing capacitance density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If trench pitch is reduced to increase capacitance density, then capacitance density is improved, but structural integrity deteriorates due to cracking and delamination
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional pillar structures that extend vertically from the conductive base layer. This vertical dimension allows capacitance to be increased without reducing the horizontal trench pitch, thereby maintaining structural integrity while achieving higher capacitance density through increased surface area in the vertical direction
Solution Approach 2:
The patent implements multiple conductive layers and dielectric layers that are stacked and wrapped around the pillar structures in a nested configuration. This nested arrangement increases the effective capacitance within the same footprint without requiring reduced pitch, as each nested layer contributes additional capacitance while sharing the same structural support
2Quantity of substance
If trench pitch is reduced to increase capacitance density, then capacitance density is improved, but manufacturing quality deteriorates due to cracking and delamination
Solution Approach 1:
By utilizing vertical pillars extending from the base layer, the design achieves higher capacitance density without compressing horizontal features to the point where manufacturing defects occur. The vertical dimension provides manufacturing tolerance buffer while maintaining precise electrical performance
3Reliability
If conventional capacitor structures are used, then structural integrity is maintained, but capacitance density is limited
Solution Approach 1:
The capacitor structure is segmented into multiple vertical pillars distributed across the conductive base layer, with each pillar containing stacked conductive and dielectric layers. This segmentation increases total capacitance through increased surface area while each individual pillar maintains structural integrity through its pillar-based geometry
Solution Approach 2:
The patent employs composite structures combining multiple conductive materials and dielectric materials in alternating layers wrapped around the pillars. This composite arrangement optimizes both electrical performance for high capacitance and mechanical properties for structural integrity, with each material layer contributing specific functional properties
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip including a conductive base layer overlying a semiconductor substrate. A plurality of conductive pillar structures vertically extending from the conductive base layer in a direction away from the semiconductor substrate. The conductive pillar structures are laterally offset from one another. A plurality of conductive layers and a plurality of capacitor dielectric layers are disposed over the conductive pillar structures. The conductive layers and the capacitor dielectric layers are stacked alternatingly with one another. The conductive layers and the capacitor dielectric layers laterally wrap around outer perimeters of the conductive pillar structures.