Semiconductor Pillar Cavities Prevent Probe Slippage
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reliable probing due to probe pin slippage during testing, which affects the accuracy and reliability of quality assessment before packaging.
Innovation Solution
The semiconductor device incorporates a pillar with cavities that prevent probe pin slippage by trapping the pin within the cavities, ensuring a secure contact for effective probing, and includes a polymer layer and redistribution layers for enhanced electrical connectivity and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional probing is performed without cavities in the pillar, then the structure is simpler, but probe pin slippage occurs during testing reducing reliability
Solution Approach 1:
The pillar is segmented by introducing cavities within its structure. These cavities divide the pillar into distinct regions, creating mechanical interlocking features that prevent probe pin slippage while maintaining overall structural integrity.
Solution Approach 2:
The cavities act as intermediary structures between the probe pin and the pillar body. They provide a mechanical interface that secures the probe pin during probing operations, eliminating direct slippage between the pin and pillar surface.
2Measurement precision
If probe pin slippage is prevented using cavities, then probing accuracy improves, but manufacturing process becomes more complex
Solution Approach 1:
The pillar fabrication process is segmented to include cavity formation as a distinct step. This allows for controlled creation of internal features that enhance probing accuracy without requiring complete redesign of the manufacturing workflow.
Solution Approach 2:
The pillar incorporates a porous or cavity-containing structure that provides mechanical anchoring for the probe pin. This porous architecture enables accurate probing while being compatible with standard semiconductor fabrication techniques for creating internal voids.
Data Source
AI summary
An apparatus comprises a pillar formed on a top surface of a semiconductor substrate, wherein the pillar comprises a first pillar region, a second pillar region and a first cavity formed between the first pillar region and the second pillar region, and wherein the first cavity is configured to accommodate a probe pin.