Semiconductor Pillar Charge Storage via Sacrificial Layer Extraction
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Solution Overview
Problem
The minimization of critical dimensions (CDs) in semiconductor devices is restricted due to the presence of capacitors in gate all around field effect transistors (GAAFETs) used in dynamic random access memories (DRAMs), which limits the reduction of line widths.
Innovation Solution
A method of manufacturing a semiconductor structure involving a support layer with multiple oxide and sacrificial layers, where an active pillar penetrates through the layer, forming annular grooves and a semiconductor oxide layer, allowing for charge storage without a traditional capacitor, enabling dual-layered stacking for improved charge storage density and reduced device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional capacitors are used in GAAFETs for charge storage, then charge storage function is achieved, but device size cannot be minimized due to capacitor occupancy
Solution Approach 1:
The patent extracts and eliminates the traditional capacitor component from the GAAFET structure. Instead of using a separate capacitor for charge storage, the invention integrates charge storage functionality directly into the semiconductor pillar through doping regions, thereby removing the space-consuming capacitor while maintaining the essential charge storage function.
Solution Approach 2:
The patent merges the charge storage function with the semiconductor pillar structure itself. By integrating doped regions (P-type and N-type) directly into the pillar, the invention combines what were previously separate components (pillar and capacitor) into a unified structure that performs both structural and charge storage functions simultaneously.
2Length of moving object
If line widths are reduced to minimize device size, then device miniaturization is achieved, but capacitor presence restricts further minimization
Solution Approach 1:
By extracting the capacitor from the device structure, the invention eliminates the geometric constraints that capacitors impose on line width minimization. Without capacitors occupying space around the pillars, further reduction of line widths and pitch becomes feasible.
Solution Approach 2:
The patent transitions from planar charge storage (requiring lateral capacitor structures) to vertical charge storage within the pillar itself through doping. This dimensional reorganization allows charge storage without lateral expansion, enabling continued miniaturization in the lateral direction.
3Quantity of substance
If charge storage density is increased to reduce device size, then storage efficiency improves, but traditional capacitor-based structures reach density limits
Solution Approach 1:
The patent applies local quality by creating highly doped regions (P-type and N-type) concentrated within the semiconductor pillar. This localized doping creates high charge carrier concentrations in specific regions, achieving high charge storage density without requiring large overall device volumes.
Solution Approach 2:
The invention uses composite doping structures within the pillar, combining P-type and N-type doped regions in a single vertical structure. This composite approach enables multiple charge storage zones within the same volume, effectively increasing charge storage density while maintaining compact dimensions.
Data Source
AI summary
A method of manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes: providing a semiconductor substrate, and forming a first bit line; forming a support layer on the semiconductor substrate, the support layer including a first oxide layer, a first sacrificial layer, a second oxide layer, a second sacrificial layer, a third oxide layer, a third sacrificial layer and a fourth oxide layer that are stacked; forming, at a position corresponding to the first bit line, an active pillar penetrating through the support layer; removing each of the first sacrificial layer and the third sacrificial layer, and forming a first trench; removing a peripheral wall of the active pillar to form a first annular groove, a size of the first annular groove being greater than a size of the first trench in a vertical direction; forming a P-type filler in the first annular groove.