Semiconductive Pillar Contact Layout for Short-Resistant Memory Cells
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Solution Overview
Problem
The challenge in semiconductor device design is to increase integration density and performance while preventing inadvertent shorting between contacts in memory devices, particularly as feature dimensions decrease, leading to increased packing density and potential electrical shorts.
Innovation Solution
The method involves forming semiconductive pillar structures with angled intervening portions to isolate contacts, using a pitch quadrupling process to reduce feature size and spacing, and transferring patterns to form digit line and storage node contacts, which reduces the likelihood of shorting and enhances contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature dimensions are reduced to increase integration density, then the number of memory cells per unit area increases, but the likelihood of inadvertent shorting between contacts increases
Solution Approach 1:
The contact structure is segmented into distinct portions: a first contact portion extending from the digit line contact region into the first opening, and a second contact portion extending from the storage node contact region into the second opening. This segmentation electrically isolates the digit line contact from the storage node contact, preventing inadvertent shorting while maintaining high integration density through the vertical pillar configuration
Solution Approach 2:
An intermediate insulating structure is introduced between the first contact portion and the second contact portion. This intermediary material electrically isolates the conductive pathways, preventing direct electrical connection between the digit line and storage node contacts while allowing the contacts to be positioned in close proximity for high-density integration
2Area of stationary object
If contact packing density is increased to reduce device area, then more contacts fit in the same space, but the separation distance between contacts decreases leading to potential shorts
Solution Approach 1:
The contact structure transitions from a planar arrangement to a vertical three-dimensional configuration. Contact portions extend vertically into openings at different heights, allowing contacts to be packed more densely in the lateral direction while maintaining adequate electrical separation through the vertical dimension and intervening insulating structures
3Area of stationary object
If digit line contact and storage node contact are positioned closer together, then device footprint is reduced, but electrical shorting between the contacts becomes more likely
Solution Approach 1:
The contact structure is divided into spatially separated contact portions: a first contact portion associated with the digit line contact and a second contact portion associated with the storage node contact. These segmented portions are positioned in different openings and at different vertical levels, reducing the device footprint while preventing electrical shorting through the spatial and vertical separation
Solution Approach 2:
An insulating intermediary structure is positioned between the first contact portion and the second contact portion. This intermediary material provides electrical isolation that prevents shorting between the digit line and storage node contacts, enabling them to be positioned closer together and reducing the overall device footprint
Data Source
AI summary
An apparatus comprises semiconductive pillar structures each individually comprising a digit line contact region disposed laterally between two storage node contact regions. At least one semiconductive pillar structure of the semiconductive pillar structures comprises a first end portion comprising a first storage node contact region, a second end portion comprising a second storage node contact region, a central portion between the first end portion and the second end portion and comprising the digit line contact region, a first intervening portion between the first end portion and the central portion, and a second intervening portion between the second end portion and the central portion. A longitudinal axis of each of the first intervening portion and the second intervening portion is oriented at an angle with respect to a longitudinal axis of the central portion. Related memory devices, electronic systems, and methods of forming the apparatus are also described.


