Semiconductor Pillar Contacts With Enlarged Silicide Interface
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Solution Overview
Problem
As semiconductor manufacturing processes advance, the smaller dimensions of components on integrated circuits lead to increased resistance in contacts or vias to vertically-oriented semiconductor structures, affecting circuit performance.
Innovation Solution
The implementation of enlarged electrically conductive regions, such as metal silicide structures, is achieved by forming semiconductor pillars with enlarged top surfaces and converting them into metal silicide, providing a larger interface area for connections and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If component dimensions are reduced to advance semiconductor manufacturing, then device integration density is improved, but contact resistance increases
Solution Approach 1:
The patent transitions from planar contact interfaces to vertically-oriented three-dimensional contact structures. By forming contacts that extend vertically along the sidewalls of semiconductor pillars rather than only at the top surface, the contact interface area is significantly increased in the vertical dimension, thereby reducing contact resistance while maintaining small footprint dimensions for high integration density.
Solution Approach 2:
The patent implements nested contact structures where conductive materials are positioned within and around semiconductor pillars. The contact structure includes inner conductive regions within the pillar and outer conductive regions surrounding the pillar, creating a nested configuration that maximizes the contact interface area within a compact volume, thus reducing resistance while preserving integration density.
2Reliability
If contact area is increased to reduce contact resistance, then electrical conductivity is improved, but device area increases
Solution Approach 1:
The patent resolves this contradiction by extending contacts vertically along the sidewalls of semiconductor pillars rather than expanding horizontally. This vertical extension increases the contact interface area for better electrical conductivity while maintaining a compact horizontal footprint, thus improving conductivity without increasing the overall device area.
Solution Approach 2:
The patent applies different contact configurations to different regions: inner contacts within pillars and outer contacts surrounding pillars. This localized differentiation allows optimization of electrical conductivity in critical regions while maintaining compact overall device dimensions, achieving high conductivity without proportionally increasing total device area.
Data Source
AI summary
A semiconductor device includes a first vertically-oriented semiconductor pillar having one or more sidewalls, and a top surface, the first vertically-oriented semiconductor pillar having a first width, a first dielectric material abutted to the one or more sidewalls of the first vertically-oriented semiconductor pillar, and a first conductive structure having a first surface, and having a second width that is greater than the first width, the first conductive structure disposed such that a second portion of its first surface is in electrical contact with the top surface of the first vertically-oriented semiconductor pillar, wherein a first portion of the first surface of the first conductive structure extends laterally beyond the top surface of the first vertically-oriented semiconductor pillar, and the second portion of the first surface is disposed on the first dielectric material.