Pillar-Type FET With Dual-Work Function Gate Electrodes
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Solution Overview
Problem
Conventional DRAM cell devices face challenges in miniaturization due to the short channel effect, leading to increased off-state drain current and leakage current, which is difficult to reduce below 1 fA, especially when trying to reduce the gate length to 70 nm or less, and existing solutions like buried channel structures and bulk FinFETs have limitations in controlling threshold voltage and leakage current.
Innovation Solution
A pillar-type field effect transistor with a semiconductor body and gate electrodes of different work functions, where the second gate electrode has a lower work function than the first, is used to reduce gate-induced drain leakage by adjusting the cross-sectional area of the semiconductor body and thickness of the gate insulating layer, thereby minimizing off-state leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the gate length is reduced to miniaturize the DRAM cell device, then the cell area and degree of integration are improved, but the off-state drain current increases due to the short channel effect
Solution Approach 1:
The patent applies local quality by forming a buried channel structure with different doping concentrations in specific regions. The channel region has a first doping concentration while the drift region has a second doping concentration lower than the first, creating localized property variations that suppress the short channel effect at the drain end while maintaining channel functionality.
Solution Approach 2:
The patent transitions from a planar channel structure to a three-dimensional buried channel structure. The channel is formed below the surface in a drift region, creating a vertical dimension for current flow that improves control over the off-state current while maintaining a miniaturized planar footprint.
2Reliability
If the doping concentration of the channel region is increased to prevent DIBL, then the threshold voltage control is improved, but the leakage current due to band-to-band tunneling increases
Solution Approach 1:
The patent implements local quality by creating distinct doping concentration zones: the channel region maintains a higher first doping concentration for threshold voltage control, while the drift region uses a lower second doping concentration to reduce band-to-band tunneling leakage current. This spatial differentiation of doping concentrations resolves the contradiction between reliability and leakage.
3Object-generated harmful factors
If a buried channel structure is used to suppress the short channel effect, then the off-state current is decreased, but the on-state current is greatly decreased due to relatively long channel length and short channel width
Solution Approach 1:
The patent uses dimensionality change by forming a buried channel that extends vertically below the surface, creating an effective channel length that is longer in the vertical dimension but maintains a compact planar footprint. This allows suppression of the short channel effect while preserving adequate on-state current through optimized vertical channel geometry.
Solution Approach 2:
The patent applies parameter changes by optimizing the depth, width, and doping concentration of the buried channel structure. By adjusting these parameters, the device achieves both low off-state current through effective channel length extension and sufficient on-state current through appropriate channel cross-sectional area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces gate-induced drain leakage and increases the threshold voltage, achieving an off-state current of 1 fA or less, while maintaining high integration and operating speed, thus overcoming the limitations of conventional DRAM cell devices.
Implementation Method 1
forming a plurality of gate electrodes having different work functions so as to lower a work function of a gate electrode in a region overlapped with a drain region
Data Source
AI summary
A pillar-type field effect transistor having low leakage current is provided. The pillar-type field effect transistor includes: a semiconductor body, source and drain formed in a semiconductor pillar; a gate insulating layer formed on a surface of the semiconductor body; a gate electrode formed on a surface of the gate insulating layer. The gate electrode includes a first gate electrode and a second gate electrode being electrically connected with the first gate electrode. The first gate electrode has a work function higher than that of the second gate electrode. Accordingly, the gate induced drain leakage (GIDL) can be reduced, so that an off-state leakage current can be greatly reduced.