Surrogate Metal Side Wall for Pillar Gate Contact
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of MOS transistors in semiconductor integrated circuits poses challenges in suppressing leak current and reducing the area occupied by the circuit, particularly due to the difficulty in forming a diffusion layer in pillar-shaped silicon layers with a polysilicon gate, which complicates the integration of a metal gate process and high-temperature processes in surrounding gate transistors (SGTs).
Innovation Solution
A method for producing SGTs through a gate-last process using two masks, where a fin-shaped and pillar-shaped semiconductor layer are formed, allowing the upper portion of the pillar-shaped semiconductor layer to function as an n-type or p-type semiconductor layer based on the work function difference between the metal and semiconductor, eliminating the need for a diffusion layer in the upper portion of the pillar-shaped semiconductor layer and simplifying the metal gate formation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a diffusion layer is formed in the upper portion of the pillar-shaped silicon layer to enable metal gate formation, then the metal gate process can be integrated with high-temperature processes, but the process complexity increases and misalignment issues arise
Solution Approach 1:
The patent applies preliminary action by forming the diffusion layer in the lower portion of the pillar-shaped silicon layer before forming the gate electrode. This allows the upper portion to remain free for subsequent metal gate formation without requiring complex diffusion layer formation steps in the upper portion, thereby integrating metal gate process with high-temperature processes while avoiding process complexity and misalignment issues.
2Manufacturing precision
If three masks are used to form silicon pillar, planar silicon layer, and gate line, then precise patterning can be achieved, but the number of process steps increases
Solution Approach 1:
The patent merges the formation of the silicon pillar and planar silicon layer into a single etching step using one mask pattern. The gate line is then formed in a subsequent step using the self-aligned structure, reducing the total number of masks and process steps while maintaining precise patterning through self-alignment effects.
3Ease of manufacture
If the upper portion of the pillar-shaped silicon layer is left without diffusion layer, then the metal gate formation is simplified, but the conductivity control in the channel region becomes challenging
Solution Approach 1:
The patent applies local quality by forming the diffusion layer only in the lower portion of the pillar-shaped silicon layer, leaving the upper portion free for metal gate formation. This localized diffusion layer formation provides sufficient conductivity control in the channel region while simplifying the metal gate formation process, as the diffusion layer is positioned where it is most effective for carrier injection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of steps required, eliminates misalignment issues, and allows for the easy formation of a metal gate SGT, enabling the upper portion of the pillar-shaped semiconductor layer to function as desired without the need for a diffusion layer, thereby improving the efficiency and simplicity of the semiconductor device production process.
Implementation Method 1
forming a metal-semiconductor compound
Implementation Method 2
the upper portion of the pillar-shaped semiconductor layer to function as an n-type or p-type semiconductor layer based on the work function difference between the metal and semiconductor
Data Source
AI summary
A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate formed of a first polysilicon; a third step of forming a second dummy gate on side walls of the first dummy gate and the pillar-shaped semiconductor layer; a fourth step of forming a side wall formed of a fifth insulating film around the second dummy gate, forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer, and forming a metal-semiconductor compound on the second diffusion layer; a fifth step of forming a gate electrode and a gate line; and a sixth step of depositing a sixth insulating film, forming a third resist for forming a contact hole on the pillar-shaped semiconductor layer, etching the sixth insulating film to form a contact hole on the pillar-shaped semiconductor layer, removing the third resist, depositing a second gate insulating film, depositing a second metal, etching back the second metal, removing the second gate insulating film on the pillar-shaped semiconductor layer so as to form a metal side wall on a side wall of an upper portion of the pillar-shaped semiconductor layer, and depositing a third metal so as to form a contact that connects an upper portion of the metal side wall to an upper portion of the pillar-shaped semiconductor layer.