Semiconductor Package Pillar Interconnects Eliminate Wire Inductance
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Solution Overview
Problem
Traditional semiconductor packages using wires and clips for connecting chips result in higher resistance, inductance, stress on devices, and environmental concerns due to lead-based solder, while also being complex and bulky.
Innovation Solution
A semiconductor package design that excludes wires and clips, utilizing pillars or lead strips, and a method involving a removable carrier, die attaching adhesive, molding encapsulations, and electrical interconnections to connect semiconductor devices, allowing for scalable, low-resistance, low-inductance, and reduced-stress assembly with enhanced thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wires and clips are used to connect chips, then electrical connections can be established, but resistance and inductance increase
Solution Approach 1:
The patent removes wires and clips from the package structure, extracting the harmful elements that cause high resistance and inductance. The connection is achieved directly through lead strips and pillar structures that are integral to the package substrate, eliminating the need for separate wire and clip components.
Solution Approach 2:
The patent merges the electrical connection function with the package substrate structure itself. Lead strips and pillars are integrated directly into the substrate, combining the functions of mechanical support and electrical connection into a single unified structure, thereby reducing parasitic inductance and resistance.
2Reliability
If traditional wire and clip connections are used, then chips can be connected, but stress is applied on semiconductor devices
Solution Approach 1:
The patent removes clips from the package structure, eliminating the mechanical stress that clips impose on semiconductor devices. Connection is achieved through integrated lead strips and pillars that provide gentle, distributed mechanical support without concentrated stress points.
3Reliability
If lead-based solder is used for die attaching, then reliable bonding is achieved, but environmental friendliness is compromised
Solution Approach 1:
The patent changes the material composition parameter by using lead-free solder instead of lead-based solder for die attaching. This substitution maintains the reliable bonding function while eliminating the environmental harm associated with lead content, complying with modern environmental regulations.
4Reliability
If wires and clips are used for connections, then electrical routing is achieved, but package form factor increases
Solution Approach 1:
The patent merges electrical connections with the package substrate structure, eliminating separate wire and clip components. Lead strips and pillars are integrated directly into the substrate, reducing the overall package volume and form factor while maintaining electrical routing functionality.
Solution Approach 2:
The patent removes wires and clips from the package structure, extracting the volume occupied by these separate components. The integrated lead strip and pillar structure requires less space, resulting in a more compact package form factor.
5Reliability
If complex wire and clip assembly is used, then connections are established, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple functions into integrated structures: lead strips and pillars serve both as mechanical support and electrical connections simultaneously. This integration simplifies the assembly process by eliminating separate steps for attaching wires and clips, reducing manufacturing complexity.
Solution Approach 2:
The patent removes wires and clips from the package structure, extracting the complex assembly steps required to install these separate components. The integrated lead strip and pillar structure can be formed directly during substrate manufacturing, significantly simplifying the overall assembly process.
Data Source
AI summary
A semiconductor package has a plurality of pillars or portions of a plurality of lead strips, a plurality of semiconductor devices, one or two molding encapsulations and a plurality of electrical interconnections. The semiconductor package excludes a wire. The semiconductor package excludes a clip. A method is applied to fabricate semiconductor packages. The method includes providing a removable carrier; forming a plurality of pillars or a plurality of lead strips; attaching a plurality of semiconductor devices; forming one or two molding encapsulations; forming a plurality of electrical interconnections and removing the removable carrier. The method may further include a singulation process.