Pillar-last TSV formation for semiconductor carrier reuse

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The existing semiconductor manufacturing process for through-silicon vias (TSVs) results in carrier warpage due to thick adhesive layers, making it unsuitable for reuse in subsequent processing stages, thereby increasing manufacturing costs and reducing efficiency.

Innovation Solution

Forming under-bump metallization features on the front side of the substrate and directly forming taller conductive pillars around exposed TSVs, allowing for a thinner adhesive layer that minimizes warpage and enables carrier reuse, eliminating the need for planarization and reducing manufacturing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a thick adhesive layer is used to attach the carrier to the substrate, then the adhesive layer can entirely surround the conductive pillars, but this causes carrier warpage that prevents carrier reuse

Engineering Contradiction:
Improveadhesive layer coverageVSAvoidcarrier reuse capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The conductive pillars are formed on the front side of the substrate before the substrate is thinned and before the carrier is attached. This preliminary formation of pillars with sufficient height ensures that when the carrier is later attached with an adhesive layer, the pillars will protrude through the adhesive layer without requiring the adhesive to be excessively thick, thereby preventing carrier warpage while ensuring proper coverage.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If conductive pillars are formed to be relatively tall (10-100 μm) above the front side of the substrate, then they can be properly electrically coupled to TSVs, but this requires a thick adhesive layer that causes carrier warpage

Engineering Contradiction:
Improveelectrical couplingVSAvoidcarrier planarity
Core Design Contradiction:
ReliabilityVSShape

Solution Approach 1:

Conductive pillars are formed in advance on the front side of the substrate with heights of 10-100 μm to ensure proper electrical coupling to TSVs. This preliminary action allows the pillars to be sufficiently tall for electrical connection while enabling the use of a thinner adhesive layer (since the pillars are already formed and will protrude through the adhesive), thereby preventing carrier warpage and maintaining carrier planarity for reuse.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If the substrate is thinned from the back side until conductive fill is exposed, then TSVs become accessible, but this requires additional processing steps and time

Engineering Contradiction:
ImproveTSV accessibilityVSAvoidprocessing time
Core Design Contradiction:
Ease of manufactureVSLoss of time

Solution Approach 1:

Conductive pillars are formed on the front side of the substrate before the substrate thinning process. This preliminary formation of pillars eliminates the need to wait for substrate thinning to expose TSVs before forming the conductive structures, as the pillars are already in place. This allows for parallel processing or more efficient sequencing of operations, reducing overall processing time while ensuring TSV accessibility.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces carrier warpage, allows for carrier reuse, and decreases manufacturing costs by eliminating unnecessary planarization and dielectric deposition steps, enhancing the efficiency and cost-effectiveness of semiconductor device production.

Implementation Method 1

the substrate has been attached to a carrier via an adhesive layer

Methodology Applied
Scientific EffectAdhesion: Adhesive

Implementation Method 2

The conductive pillars can be fabricated by a suitable electroplating or electroless plating process

Methodology Applied
Scientific EffectElectroplating: Electroplating

Implementation Method 3

The conductive pillars can be fabricated by a suitable electroplating or electroless plating process

Methodology Applied
Scientific EffectElectroless plating: Electrodeposition

Data Source

PatentUS11631630B2Pillar-last methods for forming semiconductor devices
Publication Date: 2023.04.18 MICRON TECHNOLOGY INC
  • US11631630B2 patent drawing
  • US11631630B2 patent drawing
  • US11631630B2 patent drawing

AI summary

Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.