Pillar Semiconductor Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
There is a need for semiconductor devices with higher integration and performance, specifically to reduce parasitic capacitance between electrodes of pillar-shaped semiconductor elements, which is essential for enhancing the performance and integration of surrounding gate transistors (SGTs).
Innovation Solution
A method for manufacturing a pillar-shaped semiconductor device involves forming a semiconductor pillar with impurity regions as source and drain, surrounded by a gate insulating and conductor layers, with specific steps including the formation of band-shaped impurity regions, semiconductor bases, and conductor layers to minimize capacitance, using techniques like etching, epitaxial growth, and deposition of low-dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SGT structures are used with source/drain regions and gate conductors formed on the same substrate level, then device integration is achieved, but parasitic capacitance between connecting lines increases reducing circuit performance
Solution Approach 1:
The patent positions the source/drain regions at different vertical levels (first level and second level) rather than on the same substrate plane. The first source/drain region is formed at a first level, while the second source/drain region is formed at a second level higher than the first level. This vertical stacking arrangement reduces the horizontal overlap between conductive elements, thereby minimizing parasitic capacitance between connecting lines while maintaining device integration.
2Productivity
If higher integration density is achieved through pillar-shaped structures, then chip size is reduced, but parasitic capacitance between closely spaced electrodes increases
Solution Approach 1:
The invention transitions from planar integration to three-dimensional vertical integration by forming pillar-shaped semiconductor structures with source/drain regions at different heights. The first source/drain region is positioned at a first level and the second source/drain region at a second level, creating a vertical channel structure. This approach achieves high integration density within a small footprint while reducing parasitic capacitance by minimizing horizontal electrode overlap through vertical separation.
Solution Approach 2:
The semiconductor device is segmented into multiple vertical levels with distinct source/drain regions. The first source/drain region and second source/drain region are separated in the vertical dimension, allowing independent optimization of each region's electrical characteristics and reducing mutual capacitive coupling between adjacent electrodes in the high-density integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance, enabling higher integration and performance of SGT circuits by optimizing the structure and layout of the semiconductor device, leading to improved performance and density.
Implementation Method 1
a semiconductor base that includes the first semiconductor pillar and the first impurity region and extends in a band shape in the first direction in plan view so as to connect to a bottom portion of the first semiconductor pillar
Implementation Method 2
a second insulating layer that has a hole or is made of a low-dielectric-constant material; a second conductor layer that is in contact with the first gate conductor layer... wherein the first conductor layer and the second conductor layer overlap each other at an intersection in plan view
Data Source
AI summary
On a semiconductor base that extends in a band shape in a direction (first direction) perpendicular to a line X-X′ direction (second direction) in plan view, an N+ layer, a P+ layer, and Si pillars that also extend in a band shape in the first direction are formed. Subsequently, a gate insulating layer and gate conductor layers are formed so as to surround the Si pillars. Subsequently, a contact hole whose bottom portion is in contact with the N+ layer and the P+ layer is formed in an insulating layer, and a first conductor W layer is formed at the bottom portion of the contact hole. Subsequently, an insulating layer that has a hole is formed in the contact hole. Subsequently, a second conductor W layer is formed in the line X-X′ direction so as to be connected to the gate conductor layers.