Semiconductor Pillar Memory Cell Layout for Low Capacitive Coupling
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Solution Overview
Problem
Capacitorless single-transistor DRAM memory devices face issues with erroneous reading and writing due to significant capacitive coupling between the word line and the floating body, leading to inadequate potential difference margins and challenges in achieving high performance and density.
Innovation Solution
The method involves forming a memory device with a semiconductor pillar structure, including a first and second gate conductor layer, impurity layers, and gate insulating layers, where the voltages applied to these layers are controlled to perform data write, read, and erase operations, with specific steps for forming semiconductor layers, impurity diffusion, and gate conductor formation to minimize capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a capacitorless single-transistor DRAM memory device is used, then device complexity is reduced and integration density is improved, but capacitive coupling between the word line and floating body causes erroneous reading and writing
Solution Approach 1:
The gate conductor layer is divided into two separate layers: a first gate conductor layer and a second gate conductor layer. This segmentation allows independent control of capacitive coupling effects, enabling the first layer to primarily control channel formation while the second layer controls charge storage, thereby reducing erroneous reading and writing caused by capacitive coupling between the word line and floating body
Solution Approach 2:
A gate insulating layer is introduced between the first gate conductor layer and the second gate conductor layer. This intermediary insulating layer electrically isolates the two gate conductor layers, preventing direct capacitive coupling between them while still allowing electric field penetration for charge control, thus improving data read and write accuracy
2Manufacturing precision
If the memory device structure is simplified to use a single transistor, then manufacturing precision requirements are reduced, but potential difference margin becomes insufficient
Solution Approach 1:
The gate conductor layer is segmented into two distinct layers with different functions: the first gate conductor layer primarily controls channel formation and the second gate conductor layer primarily controls charge storage. This functional segmentation allows each layer to be optimized independently, enhancing the potential difference margin between stored states while maintaining manufacturing feasibility
Solution Approach 2:
The two gate conductor layers are positioned at different locations relative to the floating body: the first gate conductor layer is closer to the channel region while the second gate conductor layer is closer to the floating body. This spatial differentiation creates local quality variations that enhance the potential difference margin by optimizing charge control at different critical interfaces
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces capacitive noise and enhances the potential difference margin, enabling stable and high-performance data storage with improved integration density in dynamic flash memory cells.
Implementation Method 1
the kinetic energy lost at this time causes generation of electron-hole pairs (impact ionization phenomenon)
Implementation Method 2
oscillation of the potential of the word line at the time of reading or writing data is directly transmitted as noise to an SGT body in a floating state because the capacitive coupling between the word line and the SGT body is large
Implementation Method 3
forming the first impurity layer at a bottom portion of the first semiconductor pillar before or after forming the first semiconductor pillar; and forming the second impurity layer at a top portion of the first semiconductor pillar before or after forming the first semiconductor pillar
Data Source
AI summary
Provided is a step of forming, on a P-layer substrate 20, an N+ layer 21A to be connected to a source line SL, Si pillars 25a to 25d, N+ layers 23A to 23D to be connected to bit lines BL1 and BL2, HfO2 layers 30a and 32 surrounding lower and upper portions of the Si pillars 25a to 25d, a TiN layer 31a to be connected to a plate line PL, and TiN layers 33a and 33b to be connected to word lines WL1 and WL2. P layers 27a to 27d are formed so as to surround the Si pillars 25a to 25d and so as to be deposited on them to form a plurality of dynamic flash memory cells arranged in rows and columns.