3D NAND Flash Memory Pillar Manufacturing via Self-Aligned Gate Formation
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Solution Overview
Problem
There is a need for higher integration density and improved performance in dynamic flash memory cells, particularly in 3D NAND flash memories where an increase in word line gate conductor layers results in decreased data read and write speed.
Innovation Solution
A method for manufacturing a semiconductor-element-containing memory device involves forming a series of insulating and material layers over a substrate, creating a pillar-shaped semiconductor layer, and integrating a donor or acceptor impurity into the semiconductor layer through a heat treatment process, followed by the formation of gate conductor layers and wiring layers to enable efficient data operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word line gate conductor layers is increased to achieve higher integration density, then the integration density is improved, but the data read and write speed deteriorates
Solution Approach 1:
The patent transitions from planar integration to three-dimensional vertical stacking by forming pillar-shaped semiconductor layers and stacking multiple memory cells in the vertical direction. This allows higher integration density without proportionally increasing the horizontal footprint, thereby maintaining data access speed by reducing the lateral distance between word lines and bit lines.
Solution Approach 2:
The patent divides the memory device into multiple independently formed pillar-shaped semiconductor layers, each containing multiple memory cells stacked vertically. This segmentation allows each pillar to be optimized for vertical integration while maintaining independent access paths, resolving the contradiction between integration density and access speed.
2Quantity of substance
If multiple insulating and material layers are formed to create pillar-shaped semiconductor layers for high integration density, then the integration density is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent forms multiple insulating and material layers in a predetermined sequence before forming the pillar-shaped semiconductor layers. This preliminary layer stacking creates self-aligned structures that simplify subsequent processing steps, such as etching and doping, thereby reducing overall manufacturing complexity despite the multi-layer structure.
Solution Approach 2:
The patent employs self-aligned formation processes where the pillar-shaped semiconductor layers and gate conductor layers automatically align with the underlying insulating and material layers during the manufacturing process. This self-alignment eliminates the need for additional alignment steps and masks, significantly reducing manufacturing complexity.
3Speed
If gate conductor layers and wiring layers are formed with high precision for improved performance, then the data read and write speed is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned formation processes where the gate conductor layers and wiring layers automatically align with the pillar-shaped semiconductor layers and underlying insulating structures during the manufacturing process. This self-alignment mechanism achieves high precision without requiring complex external alignment systems, thereby improving data read and write speeds while maintaining feasible manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the integration density and performance of dynamic flash memory cells by allowing for high precision and self-alignment in the formation of gate conductor layers and wiring electrodes, improving data read and write speeds.
Implementation Method 1
performing a heat treatment, thereby causing the first semiconductor layer and the first alloy layer to be integrated with each other to form a second alloy layer and also causing the donor impurity or the acceptor impurity of the first semiconductor layer to diffuse into the first pillar-shaped semiconductor layer
Implementation Method 2
causing the donor impurity or the acceptor impurity of the first semiconductor layer to diffuse into the first pillar-shaped semiconductor layer
Data Source
AI summary
A two-stage dynamic flash memory is formed as follows. An N+ layer 20 is formed in a pillar-shaped semiconductor layer 12, which stands on an N+ layer 2a, by performing a heat treatment, thereby producing an effect of forcing a donor impurity out into the pillar-shaped semiconductor layer 12 from a silicide layer 18, which is a layer formed to surround a middle portion of the pillar-shaped semiconductor layer 12 and contains the donor impurity. Gate oxide layers 19a to 19d are formed on a side surface of the pillar-shaped semiconductor layer 12. Etching is performed with a single mask to form first to fourth gate conductor layers 21aa, 22aa, 22ba, and 21ba and a silicide layer 18a, which have the same shape as viewed in plan view. An N+ layer 23 is formed on a top portion of the pillar-shaped semiconductor layer 12.