Pillar-Shaped NAND Flash Memory Device With Segmented Insulating Layers
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Solution Overview
Problem
Existing vertical NAND-type flash memory devices face challenges in forming tunnel insulating layers, interlayer insulation films, and word-line electrodes with high reliability and low defects, which are crucial for achieving high-density and cost-effective memory devices.
Innovation Solution
A pillar-shaped semiconductor memory device is developed with a specific structure that includes a semiconductor substrate, semiconductor pillars, tunnel insulating layers, data charge storage insulating layers, and stacked material layers with conductor layers, which isolate the interlayer insulating layers and conductor layers, allowing for reliable data writing, erasing, and retention through voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form tunnel insulating layers and interlayer insulation films in vertical NAND-type flash memory, then the basic memory structure can be achieved, but high reliability and low defect formation cannot be ensured
Solution Approach 1:
The patent segments the insulating layer formation process into distinct stages: first forming the tunnel insulating layer with specific characteristics, then forming the interlayer insulation film with different characteristics. Each layer is optimized independently for its specific function, allowing high reliability without compromising manufacturing precision. The tunnel insulating layer uses one material composition and deposition condition set, while the interlayer insulation film uses another, resolving the contradiction between reliability and defect formation.
Solution Approach 2:
The patent applies local quality by giving different regions of the memory structure different insulating layer properties. The tunnel insulating layer adjacent to the semiconductor pillar has different material composition, thickness, and deposition conditions compared to the interlayer insulation film. This localized optimization ensures each region meets its specific reliability requirements while maintaining overall manufacturing precision.
2Productivity
If vertical NAND-type flash memory structure is implemented to achieve high integration, then device density increases, but the complexity of forming reliable insulating layers and electrodes increases
Solution Approach 1:
The patent divides the complex insulating layer structure into segmented, functionally distinct layers that can be formed using standardized deposition processes. By segmenting the structure into tunnel insulating layers and interlayer insulation films with clear functional boundaries, the patent reduces process complexity while maintaining high integration density. Each segment can be optimized independently without increasing overall manufacturing complexity.
Solution Approach 2:
The patent employs universal deposition techniques that can form multiple types of insulating layers (tunnel insulating layers and interlayer insulation films) using the same equipment and process family. This multi-functionality approach allows high-density vertical NAND structure to be achieved without proportionally increasing manufacturing complexity, as the same deposition system handles different layer types with adjusted parameters.
3Adaptability or versatility
If tunnel insulating layers and interlayer insulation films are formed to surround semiconductor pillars, then memory cell functionality is achieved, but defect formation and reliability issues arise
Solution Approach 1:
The patent applies local quality by optimizing the insulating layer properties at different locations around the semiconductor pillar. The tunnel insulating layer formed directly on the pillar surface has different characteristics from the interlayer insulation film formed in the surrounding space. This localized optimization ensures memory cell functionality is achieved while minimizing defect formation in each specific region.
Solution Approach 2:
The patent performs preliminary action by carefully controlling the deposition conditions and sequence before defects can form. The tunnel insulating layer is formed first with specific parameters optimized for pillar surface coverage, followed by the interlayer insulation film with parameters optimized for gap filling and planarization. This preliminary optimization of each step prevents defect formation while maintaining functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the formation of high-reliability, high-density NAND-type flash memory elements with reduced defects, improving memory characteristics and data retention while maintaining low production costs.
Implementation Method 1
data writing and erasing due to data charge transfer between the first semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer
Implementation Method 2
a first conductor layer-forming step of forming a first conductor layer on the outer periphery of the first semiconductor pillar and above the semiconductor substrate by allowing a material atom to be incident from a direction perpendicular to an upper surface of the mask insulating layer
Data Source
AI summary
A method for producing a pillar-shaped semiconductor memory device includes forming a mask on a semiconductor substrate and etching to form a semiconductor pillar on the semiconductor substrate. A tunnel insulating layer is formed and a data charge storage insulating layer is formed so as to surround the tunnel insulating layer, and a first conductor layer and a second interlayer insulating layer are formed on the semiconductor pillar. A stacked material layer is formed in a direction perpendicular to an upper surface of the semiconductor substrate, the stacked material layer including the first conductor layer and the second interlayer insulating layer. Data writing and erasing due to charge transfer between the semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer is performed by application of a voltage to the first conductor layer.