Pillar-Shaped NAND Flash Memory Insulating Layer Formation

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Solution Overview

Problem

Existing vertical NAND-type flash memory devices face challenges in forming tunnel insulating layers, interlayer insulation films, and word-line electrodes with high reliability and low defects, which are essential for achieving high-density and cost-effective memory devices.

Innovation Solution

A pillar-shaped semiconductor memory device is designed with a semiconductor substrate, a semiconductor pillar, tunnel insulating layers, data charge storage insulating layers, and stacked material layers that include conductor layers and interlayer insulating layers, which are formed using specific deposition methods and heat treatments to ensure high reliability and low defect rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional deposition methods are used to form tunnel insulating layers and interlayer insulation films, then manufacturing process is simpler, but manufacturing precision and reliability deteriorate due to high defect rates

Engineering Contradiction:

Improvedefect rate of insulating layersVSAvoidcomplexity of deposition process

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent divides the deposition process into multiple sequential steps: forming the tunnel insulating layer first, then forming the interlayer insulation film in a subsequent step. This segmentation allows each layer to be optimized independently with appropriate deposition conditions, reducing defects while maintaining process manageability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary preparation by forming the tunnel insulating layer with specific properties before forming the interlayer insulation film. This preliminary action ensures that the substrate is properly prepared, reducing defects in the subsequent interlayer insulation film formation

Inventive Principle:

Principle #10Preliminary action

2Quantity of substance

If vertical NAND-type flash memory structure is implemented to achieve high integration, then device density is improved, but manufacturing difficulty increases due to challenges in forming reliable insulating layers

Engineering Contradiction:

Improvememory device densityVSAvoidease of forming insulating layers

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent changes deposition parameters such as temperature, pressure, and gas flow rates to optimize the formation of tunnel insulating layers and interlayer insulation films in vertical NAND structures. These parameter adjustments enable reliable film formation with reduced defects, making high-density manufacturing more feasible

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures combining tunnel insulating layers and interlayer insulation films with specific material compositions. This composite approach leverages the complementary properties of different materials to achieve both high density and manufacturability in vertical NAND flash memory devices

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables the formation of high-density, reliable NAND-type flash memory devices with improved data retention and reduced defect generation, leading to enhanced memory characteristics and cost-effectiveness.

Implementation Method 1

data writing and erasing due to data charge transfer between the first semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer

Methodology Applied

Scientific EffectQuantum tunneling:

Implementation Method 2

forming a first conductor layer on the outer periphery of the first semiconductor pillar and above the semiconductor substrate by allowing a material atom to be incident from a direction perpendicular to an upper surface of the mask insulating layer

Methodology Applied

Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS10121795B2Method for producing pillar-shaped semiconductor memory device

Publication Date: 2018.11.06 UNISANTIS ELECTRONICS SINGAPORE PTE LTD

AI summary

A method for producing a pillar-shaped semiconductor memory device includes forming a mask on a semiconductor substrate and etching to form a semiconductor pillar on the semiconductor substrate. A tunnel insulating layer is formed and a data charge storage insulating layer is formed so as to surround the tunnel insulating layer, and a first conductor layer and a second interlayer insulating layer are formed on the semiconductor pillar. S stacked material layer is formed in a direction perpendicular to an upper surface of the semiconductor substrate, the stacked material layer including the first conductor layer and the second interlayer insulating layer. Data writing and erasing due to charge transfer between the semiconductor pillar and the data charge storage insulating layer through the tunnel insulating layer is performed by application of a voltage to the first conductor layer.