Vertical Semiconductor Pillar Packing Density
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Solution Overview
Problem
Existing semiconductor devices with vertical transistors face limitations in miniaturization due to constraints on the number of semiconductor pillars that can be arranged per unit surface area, which hinders further miniaturization efforts.
Innovation Solution
The semiconductor device incorporates multiple semiconductor pillars arranged in a specific configuration with gate insulating films and electrodes, along with embedded insulating films, to increase packing density and prevent short-circuiting, allowing for more efficient miniaturization by enabling a higher number of pillars in a given area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple gate electrodes are provided on semiconductor pillars to support miniaturization, then transistor functionality is improved, but the number of pillars that can be arranged per unit surface area is limited
Solution Approach 1:
The patent transitions from planar transistor arrangement to vertical transistor architecture, where semiconductor pillars extend in the thickness direction (third dimension) of the substrate. This dimensional change allows multiple pillars to be arranged in a given surface area without increasing the planar footprint, thereby improving surface area utilization while maintaining transistor functionality.
Solution Approach 2:
The patent divides the semiconductor structure into multiple discrete pillars arranged in arrays, with each pillar containing segmented gate electrodes (first gate electrode and second gate electrode) at different height positions. This segmentation enables independent control and optimization of each pillar's functionality while maximizing the number of pillars per unit area.
2Length of moving object
If the channel length and channel width are decreased in planar transistors to achieve miniaturization, then device size is reduced, but short channel effects occur
Solution Approach 1:
The patent employs vertical transistors where the channel extends in the thickness direction rather than the planar direction. This allows the channel length to be defined by the pillar height (in the third dimension) while the channel width is determined by the pillar diameter, enabling miniaturization in the planar direction without suffering from short channel effects that plague planar transistors with reduced channel dimensions.
3Quantity of substance
If semiconductor pillars are arranged densely to support miniaturization, then packing density is improved, but short-circuiting between pillars may occur
Solution Approach 1:
The patent introduces insulating films as intermediary layers between adjacent semiconductor pillars. These insulating films are positioned in the gaps between pillars and provide electrical isolation, preventing short-circuiting while allowing dense pillar arrangement. The insulating films act as mediators that enable high packing density without compromising electrical isolation reliability.
Data Source
AI summary
One semiconductor device includes an active region extending in a first direction, and first, second, and third semiconductor pillars which are provided upright relative to a main surface of the active region and disposed side by side in succession in the first direction; and between the first semiconductor pillar and the second semiconductor pillar, a first gate insulating film in contact with a side surface of the first semiconductor pillar, a first gate electrode in contact with the first gate insulating film, a second gate insulating film in contact with a side surface of the second semiconductor pillar, a second gate electrode in contact with the second gate insulating film, and a first embedded insulating film located between the first and second gate electrodes; and between the second and third semiconductor pillars, a second embedded insulating film in contact with the side surfaces of the second and third semiconductor pillars.