3D Semiconductor Memory with Pillar Patterns and Variable Resistance Elements
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration, improved switching characteristics, and simplified manufacturing processes, particularly in the design of memory circuits for electronic devices, where existing technologies struggle with complex structures and high complexity in fabrication.
Innovation Solution
The proposed semiconductor memory device includes a substrate with line patterns and pillar patterns arranged in a matrix, source lines, word lines, interconnection lines, and variable resistance elements, where the source line is coupled to the line patterns through insulating layer openings, and bit lines are formed over the variable resistance elements, enabling efficient data storage and simplified fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional memory device structures are used, then manufacturing processes become complex, but integration degree remains limited
Solution Approach 1:
The patent transitions from planar memory structures to three-dimensional vertical structures by forming pillar patterns that extend in the vertical direction and line patterns that extend in the horizontal direction, allowing bit lines and word lines to intersect in three dimensions. This dimensional change enables higher integration without proportionally increasing manufacturing complexity.
Solution Approach 2:
The memory device is segmented into distinct functional components: pillar patterns forming vertical channels, line patterns forming horizontal channels, variable resistance elements positioned at intersections, and insulating layers separating conductive elements. This segmentation allows each component to be optimized independently while maintaining overall integration.
2Productivity
If integration degree is increased, then device density improves, but switching characteristics deteriorate
Solution Approach 1:
Variable resistance elements are selectively positioned only at the intersection points of vertical pillar patterns and horizontal line patterns, ensuring that switching characteristics are maintained precisely where needed. The insulating layers are applied locally to isolate specific conductive paths while allowing others to function, preserving switching performance in high-density configurations.
3Ease of manufacture
If manufacturing process is simplified, then fabrication difficulty reduces, but device functionality becomes limited
Solution Approach 1:
The patent employs a universal fabrication approach where insulating layers serve multiple functions: electrical isolation between conductive elements, structural support for vertical pillar patterns, and definition of horizontal line patterns. Variable resistance elements simultaneously provide switching functionality and memory storage capability. This multi-functionality simplifies the manufacturing process by reducing the number of specialized components and steps required.
Data Source
AI summary
An electronic device includes a semiconductor memory, the semiconductor memory including: a substrate configured to comprise a plurality of line patterns which are extended in a second direction, and a plurality of pillar patterns which protrude perpendicular to the line patterns and are arranged in the second direction and in a first direction crossing the second direction; a source line configured to be formed between the line patterns, to be coupled to the line patterns disposed at both sides of the source line, and to be extended in the second direction; a word line configured to be in contact with sidewalls of the pillar patterns arranged in the first direction, and to be extended in the first direction; an interconnection line configured to be disposed over the pillar patterns, and to be extended in the first direction so as to be coupled to the pillar patterns arranged in the first direction; variable resistance elements configured to be disposed over the interconnection line, and to be positioned between the pillar patterns which are adjacent to each other in the first direction; and a bit line configured to be disposed over the variable resistance elements, and to be extended in the second direction so as to be coupled to the variable resistance elements arranged in the second direction.