Backside Contact Pillar Patterning for Alignment and Void Control
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Solution Overview
Problem
As semiconductor node sizes shrink, the congestion of signal and power lines in the back-end-of-line (BEOL) region above semiconductor devices becomes significant, necessitating the development of new contact forms between backside power rails and device terminals to enable a backside power distribution network (BSPDN). Current methods, such as direct backside contacts through wafer-bonding, suffer from misalignment issues, and self-aligned processes face challenges in controlling the shape and void formation in backside contacts.
Innovation Solution
A semiconductor unit with a backside contact structure that includes sidewalls with a positive slope and a dielectric liner, formed through a process involving etching and metal filling, ensuring accurate alignment and minimizing voids, thereby providing reliable power delivery from backside power rails to semiconductor device terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If direct backside contacts through wafer-bonding are used, then power delivery is enabled, but misalignment issues occur
Solution Approach 1:
The method performs preliminary patterning of the backside contact openings and dielectric liner formation before substrate bonding. This preliminary action establishes precise alignment features that guide subsequent bonding, eliminating misalignment issues that plague direct post-bonding contact formation approaches
Data Source
AI summary
In order to achieve higher contact quality for backside power distribution networks, provided is a backside contact to a semiconductor device having a positive slope and a dielectric sidewall liner, and methods for making the same.