Pillar Select Transistor Layout for Dense 3D Cross-Point Memory

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Solution Overview

Problem

Increasing the number of memory cells in a 3-D cross point memory array proportionately increases the number of decoder transistors needed, leading to a larger overall footprint for the decoder transistors, which hinders memory density and increases production costs.

Innovation Solution

The implementation of pillar select transistors and a memory device structure where multiple memory cells in a tier are coupled through a common electrode to reduce the number of decoder transistors, while confining the decoder transistors within the footprint of a memory cell to minimize device size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of memory cells in a 3-D cross point memory array is increased, then memory density is improved, but the number of decoder transistors increases proportionately, leading to a larger decoder footprint

Engineering Contradiction:

Improvenumber of memory cellsVSAvoiddecoder transistor footprint

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

Multiple memory cells in a tier are coupled through a common electrode, merging the selection function for multiple cells into a single transistor. This reduces the number of decoder transistors needed as memory cell count increases, directly resolving the contradiction between increasing memory density and maintaining decoder footprint size.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The common electrode serves multiple memory cells simultaneously, making it a universal selection mechanism. This multi-functional approach allows a single decoder transistor to control access to multiple memory cells, reducing the proportional increase in decoder transistors when scaling up memory cell quantity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Quantity of substance

If decoder transistors are distributed across a larger area to accommodate more memory cells, then memory cell quantity increases, but device integration density decreases

Engineering Contradiction:

Improvememory cell quantityVSAvoiddecoder transistor distribution

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

By combining multiple memory cell selections through a common electrode, the decoder transistor distribution becomes more compact. This merging approach reduces the spatial spread of decoder transistors while maintaining the capability to address increased memory cell quantities.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12268011B2Pillar select transistor for 3-dimensional cross point memory

Publication Date: 2025.04.01 INTEL CORP

AI summary

A memory device structure includes a vertical transistor having a channel between a source and a drain, a gate electrode adjacent the channel, where the gate electrode is in a first direction orthogonal to a longitudinal axis of the channel. A gate dielectric layer is between the gate electrode and the channel A first terminal of a first interconnect is coupled with the source or the drain, where the first interconnect is colinear with the longitudinal axis. The memory device structure further includes a pair of memory cells, where individual ones of the memory cells includes a selector and a memory element, where a first terminal of the individual ones of the memory cell is coupled to a respective second and a third terminal of the first interconnect. A second terminal of the individual ones of the memory cell is coupled to individual ones of the pair of second interconnects.