Pillar-Shaped Semiconductor Layer Gate Structure for Flash Memory
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing capacitance between control gate lines while maintaining a high degree of integration, as the width of control gate lines increases and the distance between them decreases, affecting writing and erasing efficiencies in flash memory cells.
Innovation Solution
A semiconductor device is designed with two floating gates sandwiching a pillar-shaped semiconductor layer, where the control gate line surrounds the floating gates and is formed on an inter-polysilicon insulating film outside the floating gates, allowing for increased distance between control gate lines and reduced capacitance, while maintaining high integration by using symmetrical arrangements and orthogonal linear masks for fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the control gate line surrounds the floating gate in conventional SGT flash memory cells, then the capacitance between the floating gate and control gate is increased, but the width of control gate lines increases and the distance between control gate lines decreases, which increases the capacitance between control gate lines and reduces the degree of integration
Solution Approach 1:
The control gate line is segmented into two separate control gates that are positioned on opposite sides of the pillar-shaped semiconductor layer. This segmentation allows each control gate to be independently positioned, increasing the distance between control gates and reducing parasitic capacitance while maintaining the surrounding gate functionality for efficient writing and erasing operations
Solution Approach 2:
The control gates are positioned in different spatial dimensions around the pillar-shaped semiconductor layer, transitioning from a single planar control gate line to multiple control gates distributed in three-dimensional space. This dimensional change allows for increased separation between control gates while maintaining effective capacitance coupling with the floating gate
2Reliability
If the control gate line width is increased to ensure proper surrounding coverage, then the capacitance between floating gate and control gate is improved, but the distance between adjacent control gate lines decreases, increasing parasitic capacitance between control gate lines
Solution Approach 1:
The continuous control gate line is divided into multiple discrete control gates positioned around the pillar-shaped semiconductor layer. This segmentation reduces the continuous width of control gate material, thereby reducing parasitic capacitance between adjacent control gates while maintaining sufficient capacitance coupling with the floating gate through strategic positioning
Solution Approach 2:
Different regions of the control gate structure have different properties: the control gates are positioned to provide strong capacitive coupling with the floating gate where needed, while maintaining increased separation in regions where parasitic capacitance between control gates is a concern. This local optimization of control gate positioning and dimensions resolves the contradiction
Data Source
AI summary
A semiconductor device includes a pillar-shaped silicon layer including a first diffusion layer, a channel region, and a second diffusion layer formed in that order from the silicon substrate side, floating gates respectively disposed in two symmetrical directions so as to sandwich the pillar-shaped silicon layer, and a control gate line disposed in two symmetrical directions other than the two directions so as to sandwich the pillar-shaped silicon layer. A tunnel insulating film is formed between the pillar-shaped silicon layer and each of the floating gates. The control gate line is disposed so as to surround the floating gates and the pillar-shaped silicon layer with an inter-polysilicon insulating film interposed therebetween.