Pillar-Shaped Semiconductor Device Manufacturing Method
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Solution Overview
Problem
There is a need for higher-density pillar-shaped semiconductor devices, particularly surrounding gate transistors (SGTs), to achieve greater integration and performance in semiconductor devices.
Innovation Solution
A method for manufacturing pillar-shaped semiconductor devices involves a series of steps including forming mask material layers, etching semiconductor pillars, and depositing and planarizing material layers to create multiple semiconductor pillars with gate insulating and conductor layers, allowing for high-density circuit formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar MOS transistor structures are used, then manufacturing processes are simple, but device density and integration level are limited
Solution Approach 1:
The patent transitions from planar two-dimensional transistor structures to three-dimensional pillar-shaped structures with vertical channels. This dimensional change allows multiple channels to be stacked vertically, significantly increasing device density while maintaining a compact footprint on the substrate.
Solution Approach 2:
The patent implements surrounding gate structures where gate electrodes wrap around the channel region in multiple layers. This nested configuration allows the gate to control the channel from multiple directions, improving device performance while enabling higher integration density.
2Quantity of substance
If pillar-shaped semiconductor devices are formed, then device density increases, but manufacturing process complexity increases
Solution Approach 1:
The patent divides the pillar formation process into multiple stages: first forming initial pillars, then selectively removing portions, and finally forming additional pillars in the removed regions. This segmentation of the manufacturing process enables precise control over pillar placement and reduces overall process complexity.
Solution Approach 2:
The patent performs preliminary etching to form first band-shaped semiconductor pillars and preliminary deposition to form material layers before final pillar formation. These preliminary actions prepare the structure in advance, making the subsequent formation of high-density pillar structures more manageable and less complex.
3Manufacturing precision
If multiple etching and deposition steps are performed, then manufacturing precision improves, but production time increases
Solution Approach 1:
The patent combines multiple operations into integrated process steps. For example, mask material layers are formed and then used for multiple etching operations, and material layers are deposited and planarized in sequence to create multiple pillars simultaneously. This merging reduces the total number of discrete steps while maintaining precision.
Solution Approach 2:
The patent maintains continuous process flow where each step builds upon the previous one without interruption. Etching, deposition, and planarization are performed in a continuous sequence, eliminating idle time between operations and reducing overall production time while preserving manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the formation of high-density pillar-shaped semiconductor devices, enhancing integration and performance by allowing for more efficient use of semiconductor material and improved circuit design flexibility.
Implementation Method 1
etching the semiconductor layer using the first mask material layer as a mask to form a first band-shaped semiconductor pillar
Implementation Method 2
forming a first material layer so as to cover the first mask material layer, the first band-shaped semiconductor pillar, and a portion of the substrate
Implementation Method 3
planarizing the first material layer and the second material layer such that upper surfaces thereof are located at the same height as an upper surface of the first mask material layer
Data Source
AI summary
A band-shaped Si pillar having a mask material layer on the top portion thereof is formed on a P+ layer. SiGe layers having mask material layers on the top portions thereof are then formed in contact with the side surfaces of the band-shaped Si pillar and the surfaces of N+ layers and the P+ layer. Si layers having mask material layers on the top portions thereof are then formed in contact with the side surfaces of the SiGe layers and the surfaces of the N+ layers. The outer peripheries of the bottom portions of the Si layers are then removed using the mask material layers as a mask to form band-shaped Si pillars. The mask material layers and the SiGe layers are then removed. Si pillars separated in the Y direction are then formed in the band-shaped Si pillars.