Pillar-Shaped Semiconductor Device for High-Density SRAM
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Solution Overview
Problem
There is a demand for semiconductor devices with higher density, performance, and reduced cost, particularly in SGT-including LSI circuits, which require innovative designs for pillar-shaped semiconductor structures to enhance integration and connectivity.
Innovation Solution
A pillar-shaped semiconductor device is designed with multiple semiconductor pillars and strategically formed contact holes and conductor layers, allowing for efficient connection of wiring layers within memory cells, achieving high-density SRAM cell circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar MOS transistor structures are used, then manufacturing processes are simple, but device density and integration are limited
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional pillar structures with vertical channels extending perpendicular to the substrate surface. This dimensional change enables multiple channels to be stacked vertically, dramatically increasing device density while maintaining manufacturability through established semiconductor processing techniques adapted for vertical geometry.
Solution Approach 2:
The pillar structure is segmented into distinct functional regions including source/drain regions, channel regions, and gate regions wrapped around the channel. This segmentation allows independent optimization of each region's properties and facilitates modular manufacturing processes where each segment can be formed through targeted material deposition and etching steps.
2Area of stationary object
If pillar-shaped SGT structures are implemented to increase density, then chip area is reduced, but connection and wiring complexity increases
Solution Approach 1:
The gate structure is nested around the vertical channel in a cylindrical configuration, with the gate insulating layer and gate electrode wrapping concentrically around the channel. This nested geometry enables compact three-dimensional integration where control lines are positioned radially around the channel, reducing the planar footprint while maintaining effective gate control.
Solution Approach 2:
Gate insulating layers serve as intermediary structures between the gate electrode and the semiconductor channel, enabling electrical isolation while maintaining mechanical and structural continuity. These intermediary layers facilitate the complex three-dimensional connections by providing isolation barriers that allow dense routing of interconnects without direct electrical interference.
3Productivity
If multiple contact holes and conductor layers are formed to connect wiring layers, then integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
Impurity regions are formed in advance during the pillar structure fabrication process, creating pre-positioned connection points that guide subsequent contact hole formation. This preliminary action establishes the spatial coordinates for interconnect routing before wiring layers are deposited, reducing alignment complexity and enabling higher integration through automated processing.
Data Source
AI summary
In an SRAM cell circuit, an N+ layer 12a and a P+ layer 13a, which are present between first gate connection W layers 22a and 22b connecting to gate TiN layers 23a and 23b in plan view, which connect to the bottom portions of Si pillars 11a and 11b, and which extend in the horizontal direction, connect through a second gate connection W layer 29a to a first gate connection W layer 22c, which connects to the gate TiN layers 23a and 23b and extend in the horizontal direction. The second gate connection W layer 29a has a bottom portion within the first gate connection W layer 22c, and has an upper surface positioned lower than the upper surfaces of the gate TiN layers 23a to 23f and the first gate connection W layers 22a to 22d.