Pillar-Shaped Semiconductor Memory Device for High-Density SRAM
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need for increased density and performance in SRAM cell circuits, particularly in semiconductor memory devices, as existing technologies struggle to achieve high-density and high-speed configurations using surrounding gate MOS transistors (SGTs).
Innovation Solution
A pillar-shaped semiconductor memory device is designed with multiple semiconductor pillars and a specific configuration of impurity regions, gate insulating layers, and gate conductor layers, along with interlayer insulating layers and wiring conductor layers, to form a high-density SRAM cell circuit. This configuration includes multiple SGTs connected through a limited number of contact holes, allowing for efficient integration and performance enhancement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple SGTs are integrated in separate semiconductor pillars to increase density, then the integration density improves, but the number of contact holes and wiring layers increases, leading to increased device complexity
Solution Approach 1:
Multiple SGTs that would traditionally require separate contact holes and wiring connections are merged into a single shared contact hole structure. The gate electrode extends continuously across multiple semiconductor pillars, allowing multiple transistors to share common electrical connections, thereby reducing the number of contact holes and wiring layers while maintaining high integration density
Solution Approach 2:
A single contact hole serves multiple functions by providing electrical connection to multiple SGTs simultaneously. The gate electrode structure performs multiple functions by acting as both the gate for individual SGTs and as an interconnect element that replaces traditional wiring layers, reducing overall device complexity
2Quantity of substance
If the SRAM cell circuit area is reduced to increase density, then integration density improves, but the performance and speed of the circuit may deteriorate
Solution Approach 1:
The patent transitions from planar two-dimensional layout to three-dimensional vertical architecture. SGTs are formed in vertically extending semiconductor pillars with gate electrodes surrounding the channels in three dimensions. This vertical stacking allows multiple transistors to be packed into a smaller planar area while maintaining adequate channel lengths and gate control, thus preserving circuit performance while achieving higher density
Data Source
AI summary
A method for producing a pillar-shaped semiconductor device includes, forming a first semiconductor pillar, a second semiconductor pillar, and a third semiconductor pillar on a substrate. A gate insulating layer and gate conductor layer are formed surrounding each of the pillars and impurity regions are formed in each pillar. The gate conductor layer is selectively processed to form gate conductors around the pillars and to interconnect the gate conductors.