Pillar-Shaped Semiconductor Device With Surrounding Gate
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Solution Overview
Problem
The density and performance of CMOS inverter circuits with surrounding gate transistors (SGTs) are limited by mask design constraints, resistance issues, large coupling capacitances, and increased circuit area due to thin gate and sidewall nitride films.
Innovation Solution
A method for producing pillar-shaped semiconductor devices involves forming semiconductor pillars with impurity regions and conductivity layers, using specific material layers and etching processes to reduce resistance and capacitance, and optimizing the structure to increase density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If thin gate and sidewall nitride films are used to reduce capacitance, then coupling capacitance is reduced, but circuit area increases
Solution Approach 1:
The patent forms a lower alloy layer that surrounds the semiconductor pillar and is connected to the drain region, with the drain region nested within the alloy layer structure. This nested configuration reduces the horizontal space required while maintaining low resistance and capacitance performance.
Solution Approach 2:
The patent transitions from planar 2D layout to 3D vertical structure by forming alloy layers that surround the semiconductor pillar in multiple dimensions. The lower alloy layer extends beneath the gate structure, utilizing the vertical dimension to reduce coupling capacitance without increasing planar circuit area.
2Productivity
If mask design constraints are relaxed to increase density, then manufacturing precision deteriorates
Solution Approach 1:
The patent performs preliminary actions by forming the lower alloy layer and impurity regions before final gate structure formation. This sequence allows subsequent layers to be self-aligned to previously formed structures, reducing mask alignment constraints and enabling higher density without sacrificing precision.
Solution Approach 2:
The patent employs self-aligned formation methods where previously deposited layers serve as masks for subsequent patterning steps. The lower alloy layer and impurity regions automatically define the positions of subsequent structures, eliminating the need for additional mask alignments and improving both density and precision.
3Reliability
If resistance is reduced by modifying impurity regions, then manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of the lower alloy layer with the formation of the drain region by using the same impurity introduction process. The alloy layer and doped region are created simultaneously through a single manufacturing step, reducing overall process complexity while achieving low resistance.
Solution Approach 2:
The lower alloy layer serves multiple functions: it acts as a low-resistance contact to the drain region, provides mechanical support, and serves as a mask for subsequent patterning steps. This multi-functionality reduces the need for separate structures and simplifies the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the density and performance of CMOS inverter circuits by reducing resistance and capacitance, allowing for higher density and faster operation without increasing circuit area.
Implementation Method 1
a first region of the first material layer that surrounds the first semiconductor pillar in plan view is formed below the second material layer, and a second region of the first material layer that is partly connected to the first region in plan view is formed below the third material layer
Data Source
AI summary
The method for producing a pillar-shaped semiconductor device includes a step of providing a structure that includes, on an i layer substrate, a Si pillar and an impurity region located in a lower portion of the Si pillar and serving as a source or a drain, a step of forming a SiO2 layer that extends in a horizontal direction and is connected to an entire periphery of the impurity region in plan view, a step of forming a SiO2 layer on the SiO2 layer such that the SiO2 layer surrounds the Si pillar in plan view, a step of forming a resist layer that is partly connected to the SiO2 layer in plan view, and a step of forming a SiO2 layer by etching the SiO2 layer below the SiO2 layer and the resist layer using the SiO2 layer and the resist layer as masks.