Pillar-Shaped Semiconductor Device Vertical Wiring Integration
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Solution Overview
Problem
There is a demand for higher density and performance in pillar-shaped semiconductor devices, particularly in three-dimensional transistors like surrounding gate transistors (SGTs), which require efficient methods for forming wiring conductor layers and contact regions to enhance integration density.
Innovation Solution
A method for producing pillar-shaped semiconductor devices involves a stack structure with semiconductor pillars, gate insulating and conductor layers, and specific steps for forming contact regions, conductor layers, and insulating layers to achieve high-density integration, including the use of metal or alloy wiring conductor layers and single-crystal semiconductor layers for improved connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wiring conductor layers are formed to connect to multiple impurity regions and gate conductor layers at different heights, then connectivity and integration are improved, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes vertical stacking to arrange multiple wiring conductor layers and semiconductor pillars in the thickness direction, enabling three-dimensional integration. This dimensional transition from planar to vertical architecture allows multiple connections without increasing lateral footprint, resolving the contradiction between connectivity and manufacturing complexity by organizing conductors across different height levels rather than spreading them horizontally
2Area of stationary object
If multiple wiring conductor layers are stacked vertically to increase integration density, then chip size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the wiring conductor layers into multiple discrete stacked layers, each serving specific connection functions. By segmenting the conductor system into separate horizontal planes at different heights, the patent enables independent formation and alignment of each layer, reducing the overall manufacturing precision burden compared to forming all connections in a single complex step
3Productivity
If pillar-shaped semiconductor structures are used to increase device density, then integration density is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent employs a unified stack structure where semiconductor pillars, gate insulating layers, gate conductor layers, and wiring conductor layers are integrated into a common vertical architecture. This multi-functional stack design allows single processing steps to simultaneously form multiple components, reducing overall manufacturing process complexity despite the increased integration density achieved through the pillar shape
Data Source
AI summary
A method for producing a pillar-shaped semiconductor device includes forming, above a NiSi layer serving as a lower wiring conductor layer and connecting to an N+ layer of an SGT formed within a Si pillar, a first conductor W layer that extends through a NiSi layer serving as an upper wiring conductor layer and connecting to a gate TiN layer and that extends through a NiSi layer serving as an intermediate wiring conductor layer and connecting to an N+ layer; forming an insulating SiO2 layer between the NiSi layer and the W layer; and forming a second conductor W layer so as to surround the W layer and have its bottom at the upper surface layer of the NiSi layer, to achieve connection between the NiSi layer and the NiSi layer.