Pillar-Shaped Semiconductor Device Wiring Integration
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Solution Overview
Problem
There is a demand for higher density and performance in pillar-shaped semiconductor devices, particularly in three-dimensional transistors like surrounding gate transistors (SGTs) which require efficient methods for forming wiring conductor layers, contact holes, and wiring metal layers to achieve increased integration.
Innovation Solution
A method for producing pillar-shaped semiconductor devices involves a stack structure with semiconductor pillars, gate insulating and conductor layers, impurity regions, and multiple wiring conductor layers that overlap in plan view, with specific steps for forming contact regions, insulating layers, and conductor layers to achieve high-density integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple wiring conductor layers are formed to connect overlapping semiconductor structures, then connectivity between stacked SGTs is improved, but manufacturing complexity increases
Solution Approach 1:
The wiring connection is divided into multiple conductor layers (first wiring conductor layer, second wiring conductor layer, third wiring conductor layer) that are formed at different heights. Each layer connects to specific impurity regions (first impurity region, second impurity region) of stacked SGTs, allowing independent formation and connection of each wiring segment to reduce overall manufacturing complexity while ensuring reliable connectivity.
Solution Approach 2:
The patent transitions from planar wiring to three-dimensional stacked wiring structures. Multiple wiring conductor layers are formed at different vertical heights to connect overlapping semiconductor structures in the vertical dimension, enabling connectivity between stacked SGTs that occupy the same planar area but different vertical positions.
2Quantity of substance
If SGTs are stacked within a single Si pillar to increase density, then integration density is improved, but wiring connection difficulty increases
Solution Approach 1:
Multiple SGTs are stacked and nested within a single Si pillar structure. The first SGT and second SGT are positioned at different vertical levels within the same pillar, with their respective impurity regions (first impurity region, second impurity region) arranged in a nested configuration. This allows high integration density while maintaining access to each SGT's connection points.
Solution Approach 2:
The patent introduces intermediate wiring conductor layers and contact structures that mediate connections between stacked SGTs. The first wiring conductor layer connects to the first impurity region, the second wiring conductor layer connects to the second impurity region, and these intermediate wiring structures facilitate connections without requiring direct access to each SGT, thereby reducing wiring connection difficulty.
3Area of stationary object
If wiring conductor layers are formed at the same height as source/drain regions, then planar area is reduced, but vertical connection requirements increase
Solution Approach 1:
The patent utilizes the vertical dimension to resolve the conflict between planar area reduction and connection requirements. Multiple wiring conductor layers are formed at different vertical heights (first wiring conductor layer at a first height, second wiring conductor layer at a second height, third wiring conductor layer at a third height), allowing connections to be made in three-dimensional space rather than requiring all connections at the same planar level.
Solution Approach 2:
The wiring connection system is segmented into multiple conductor layers, each responsible for connecting to specific impurity regions at different heights. This segmentation allows the wiring structure to be formed in discrete steps, with each layer connecting to its target impurity region independently, thereby managing vertical connection requirements systematically while minimizing planar area usage.
Data Source
AI summary
A method for producing a pillar-shaped semiconductor device includes forming, above a NiSi layer serving as a lower wiring conductor layer and connecting to an N+ layer of an SGT formed within a Si pillar, a first conductor W layer that extends through a NiSi layer serving as an upper wiring conductor layer and connecting to a gate TiN layer and that extends through a NiSi layer serving as an intermediate wiring conductor layer and connecting to an N+ layer; forming an insulating SiO2 layer between the NiSi layer and the W layer; and forming a second conductor W layer so as to surround the W layer and have its bottom at the upper surface layer of the NiSi layer, to achieve connection between the NiSi layer and the NiSi layer.