Semiconductor Pillar Sidewall Structure for Contact Reliability
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Solution Overview
Problem
Conventional semiconductor devices with surrounding gate transistors (SGTs) face challenges in suppressing leak currents and achieving high integration due to difficulties in forming contacts, which often result in short-circuiting and wide diffusion layers, especially as transistor sizes decrease.
Innovation Solution
A semiconductor device with a laminated sidewall structure comprising an insulating film and polysilicon on the upper sidewall of the pillar-shaped silicon layer, which reduces etching rates and allows for a deeper diffusion layer without lateral widening, enabling efficient contact formation and lower resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional SGT manufacturing method with nitride film sidewall is used, then the structure can be formed, but the etching selection ratio decreases and short-circuiting occurs between contact and gate
Solution Approach 1:
The patent divides the sidewall structure into two distinct segments: a lower nitride film sidewall and an upper oxide film sidewall. This segmentation allows each material to perform its function optimally - the nitride film provides etching protection in the lower region where high selection ratio is needed, while the oxide film provides etching protection in the upper region where the contact hole should terminate, preventing short-circuiting to the gate.
Solution Approach 2:
The patent introduces an intermediary oxide film layer between the nitride film sidewall and the gate structure. This oxide film acts as a mediator that stops the contact hole etching process before it reaches the gate, preventing short-circuiting while allowing the nitride film to maintain its etching protection function in the lower region.
2Length of moving object
If ion implantation is performed to form deep diffusion layer, then the diffusion layer depth increases, but the diffusion layer widens laterally reducing integration density
Solution Approach 1:
The patent applies local quality by forming a shallower diffusion layer in the upper portion of the silicon pillar where the channel is located, while maintaining adequate doping in the lower portion. This localized doping strategy prevents lateral widening in the critical upper region where channel control is needed, thereby maintaining high integration density while ensuring proper transistor operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively decreases resistance in the upper portion of the silicon pillar, prevents short-circuiting, and allows for higher integration by forming a shallow junction and enabling impurity implantation into the polysilicon sidewall, thus improving the performance of SGTs.
Implementation Method 1
It is known that oxide film etching for forming a contact has a high selection ratio to a nitride film in a flat portion, but the selection ratio in a nitride film shoulder portion is lower than that in the flat portion.
Implementation Method 2
the diffusion layer is formed in an upper portion of the silicon pillar by ion implantation
Data Source
AI summary
A semiconductor device includes a pillar-shaped silicon layer. A sidewall having a laminated structure including an insulating film and silicon resides on an upper sidewall of the pillar-shaped silicon layer. The silicon of the sidewall is electrically connected to a top of the pillar-shaped silicon layer.