3D Semiconductor Pillar Silicide Formation for Integration Density
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Solution Overview
Problem
Current methods for manufacturing 3D semiconductor integrated circuit devices, particularly using 3D transistors as access devices in variable resistive memory devices, face challenges in improving operation current and integration density.
Innovation Solution
A method involving the formation of pillars in a semiconductor substrate with specific insulating and silicide layers, along with high concentration impurity regions and a silicide layer formation process, to enhance the structure and performance of the semiconductor integrated circuit device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D vertical channel structure transistors are used to increase integration density, then integration density is improved, but operation current deteriorates
Solution Approach 1:
The patent applies local quality by forming high concentration impurity regions specifically at the drain and source portions of the pillar structure, while maintaining a different doping concentration in the channel region. This localized doping strategy optimizes carrier concentration where needed (at contacts) without compromising the vertical channel functionality, thereby improving operation current while maintaining integration density.
Solution Approach 2:
The patent implements preliminary action by forming the high concentration impurity regions in the drain and source areas before final device operation. This pre-formed high concentration doping prepares low resistance contact regions in advance, ensuring good ohmic contact and sufficient operation current from the beginning of device operation.
2Reliability
If silicide layer is formed over the upper portion of pillars, then contact resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges the silicide formation process with the existing metal electrode formation process. The silicide layer is formed as part of the same manufacturing sequence that creates the metal electrodes, combining two functions (contact resistance reduction and electrode formation) into a unified process flow, thereby reducing manufacturing complexity while still achieving low contact resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the operation current and integration density of 3D semiconductor integrated circuit devices by optimizing the structure of pillars and silicide layer formation, reducing contact resistance and facilitating efficient manufacturing processes.
Implementation Method 1
performing heat treatment to react the conductive layer and the second high concentration impurity region to form a silicide layer
Data Source
AI summary
A method of manufacturing a semiconductor integrated circuit device is provided. The method includes forming a plurality of pillars in a semiconductor substrate, forming an insulating layer between the plurality of pillars in such a manner that an upper region of each pillar protrudes, forming a silicide layer on an exposed surface of the pillar, and forming an insulating layer for planarization in a space between pillars.