Semiconductor Pillar Epitaxial Layer Silicide Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor device manufacturing is the difficulty in forming an adequate silicide layer on pillar-shaped silicon layers due to the 'narrow width effect,' which increases interface resistance and leads to short-channel effects and short-circuiting issues in Surrounding Gate Transistors (SGTs).
Innovation Solution
The solution involves forming an epitaxial semiconductor layer on top of the pillar-shaped silicon layers, which increases the surface area for the silicide layer, reducing the narrow width effect and interface resistance, and using a larger silicide layer to prevent short-circuiting by overetching during contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pillar-shaped silicon layer is formed with a sufficiently small size to suppress short-channel effects, then channel controllability is improved, but the narrow width effect increases and makes it difficult to form an adequate silicide layer
Solution Approach 1:
The patent transitions from a two-dimensional planar contact structure to a three-dimensional structure by forming an epitaxial semiconductor layer on top of the pillar-shaped silicon layer. This vertical extension creates additional surface area for silicide formation, allowing adequate silicide layer formation even when the pillar diameter is reduced for better channel controllability.
2Reliability
If the pillar-shaped silicon layer size is reduced to suppress short-channel effects, then transistor performance is improved, but interface resistance between silicide and diffusion layer increases
Solution Approach 1:
By forming an epitaxial semiconductor layer vertically on top of the pillar-shaped silicon layer, the patent increases the contact area between the silicide layer and the diffusion layer. This vertical extension compensates for the reduced lateral dimensions, maintaining low interface resistance even when the pillar diameter is minimized for superior transistor performance.
3Productivity
If dimensional shrinking is performed during dry etching to reduce pillar size, then integration density is improved, but the narrow width effect on silicide layer formation worsens
Solution Approach 1:
The patent compensates for the narrow width effect caused by dimensional shrinking by extending the structure vertically through epitaxial layer growth. This vertical extension provides sufficient surface area for silicide formation even when the pillar lateral dimensions are reduced to achieve higher integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor characteristics by reducing parasitic resistance and preventing short-circuiting between the contact and gate, improving the overall performance and reliability of SGTs.
Implementation Method 1
forming an epitaxial semiconductor layer on top of the pillar-shaped silicon layers
Data Source
AI summary
It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; a bottom doped region formed in contact with a lower part of the semiconductor pillar; a first gate formed around a sidewall of the semiconductor pillar through a first dielectric film therebetween; and a top doped region formed so as to at least partially overlap a top surface of the semiconductor pillar, wherein the top doped region has a top surface having an area greater than that of the top surface of the semiconductor pillar.