Wafer-Level Package Pillar Structure Mitigates Solder Bump Cracking
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Solution Overview
Problem
Wafer-level packaging techniques face limitations when applied to larger integrated circuit chips due to thermal expansion mismatches between chips and printed circuit boards, leading to stress and cracking in solder bumps during thermal cycling and electrical migration tests.
Innovation Solution
Incorporating an inner pillar structure within the solder bump assemblies, which can be fabricated using copper, to extend into the solder bumps and act as a physical barrier against crack propagation, thereby reducing stress and enhancing the solder joint's strength and fatigue life.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If wafer-level packaging is applied to larger integrated circuit chips, then the chip size and solder bump array size can be increased, but thermal expansion mismatches cause stress and cracking in solder bumps during thermal cycling
Solution Approach 1:
The solder bump assembly is segmented into multiple components: a solder bump, an intermediate layer, and a pillar structure. This segmentation allows each component to have different material properties and functions, with the pillar structure specifically designed to accommodate thermal expansion differences and prevent crack propagation in larger chips
Solution Approach 2:
The solder bump assembly uses composite materials with different properties: the solder bump provides electrical connection, the intermediate layer provides barrier and adhesion functions, and the pillar structure (made of copper or copper alloy) provides mechanical support and stress relief. This composite structure resolves the thermal expansion mismatch problem while maintaining reliability
2Area of stationary object
If wafer-level packaging is applied to larger integrated circuit chips, then the chip size and solder bump array size can be increased, but electrical migration tests result in cracking of solder bumps
Solution Approach 1:
The solder bump assembly is segmented into multiple components: a solder bump, an intermediate layer, and a pillar structure. This segmentation allows each component to have different material properties and functions, with the pillar structure specifically designed to accommodate thermal expansion differences and prevent crack propagation in larger chips
Solution Approach 2:
The solder bump assembly uses composite materials with different properties: the solder bump provides electrical connection, the intermediate layer provides barrier and adhesion functions, and the pillar structure (made of copper or copper alloy) provides mechanical support and stress relief. This composite structure resolves the thermal expansion mismatch problem while maintaining reliability
3Ease of manufacture
If traditional solder bump structures are used, then the manufacturing process is simple, but the solder joints lack strength and fatigue resistance under thermal stress
Solution Approach 1:
The solder bump assembly is segmented into multiple components: a solder bump, an intermediate layer, and a pillar structure. This segmentation allows each component to have different material properties and functions, with the pillar structure specifically designed to accommodate thermal expansion differences and prevent crack propagation in larger chips
Solution Approach 2:
The solder bump assembly uses composite materials with different properties: the solder bump provides electrical connection, the intermediate layer provides barrier and adhesion functions, and the pillar structure (made of copper or copper alloy) provides mechanical support and stress relief. This composite structure resolves the thermal expansion mismatch problem while maintaining reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The pillar structure effectively mitigates thermal stress and electrical migration issues, allowing for larger solder bump arrays and improving the reliability and durability of wafer-level package devices.
Implementation Method 1
A solder ball is placed onto the pillar structure and reflowed over the pillar structure and the bump interface to form a solder bump
Data Source
AI summary
Wafer-level package (semiconductor) devices are described that have a pillar structure that extends at least partially into a solder bump to mitigate thermal stresses to the solder bump. In implementations, the wafer-level package device may comprise an integrated circuit chip having a surface and a solder bump disposed over the surface. The wafer-level package device may also include a pillar structure disposed over the surface that extends at least partially into the solder bump.


