Pillar Memory String Structure for Dense 3D Nonvolatile Memory
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in achieving high integration and large capacity due to difficulties in reducing design rules, requiring complex photo etching processes and leading to increased costs and variations in transistor properties, especially with three-dimensional memory cells using a SGT structure, which can result in short circuits and large cell areas.
Innovation Solution
A nonvolatile semiconductor memory device with memory strings comprising pillar-shaped semiconductors, insulation films, and electrodes arranged in a two-dimensional conductor layer configuration, along with a manufacturing method that includes forming diffusion areas, insulation films, and pillar-shaped semiconductors to enhance integration and reduce complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If design rules are reduced to proceed high integration, then integration degree increases, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell layouts to three-dimensional stacked memory cell structures. Multiple memory cell layers are stacked vertically, allowing high integration without requiring further reduction of lateral design rules. This vertical stacking enables continued productivity improvement while maintaining manufacturing precision in the lateral dimensions.
2Productivity
If critical photo etching processes are increased to achieve three-dimensional memory cell structure, then integration degree increases, but device complexity increases
Solution Approach 1:
The three-dimensional memory cell structure is segmented into multiple identical layers stacked vertically. Each layer contains memory cells with the same structure, allowing standardized manufacturing processes to be repeated across layers. This segmentation reduces overall device complexity by using modular, repeatable units rather than requiring complex unique structures for each cell.
Solution Approach 2:
Multiple memory cell layers are nested vertically, with each layer containing complete memory cell structures including pillars, gates, and insulating films. The nested stacking allows high integration while maintaining relatively simple individual layer structures that can be manufactured using standard processes.
3Reliability
If pillar diameter is increased to avoid short circuits, then reliability improves, but cell area increases
Solution Approach 1:
The patent uses vertical stacking of multiple memory cell layers to achieve high integration without increasing lateral cell area. By moving to three-dimensional stacking, the design can maintain small pillar diameters for high density while ensuring reliability through proper vertical isolation and gate structure design, rather than relying on large lateral spacing.
Data Source
AI summary
A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.