Semiconductor Pillar Terminal Vertical Contact
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Solution Overview
Problem
Conventional wire bonding technologies for stacked semiconductor chips face challenges such as size limitations, signal delay, and complex fabrication due to the need for exposed terminals and varying chip sizes, which hinder the development of compact, high-integration semiconductor packages.
Innovation Solution
A semiconductor device with a first chip substrate made of semiconductor material and a second chip substrate made of insulating material, featuring pillar-shaped terminals penetrating the insulating substrate and pad-shaped terminals on its surface, allowing for direct electrical connections without the need for wire bonding, thereby reducing package size and enhancing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding technology is used to couple stacked semiconductor chips, then electrical connections between chips are achieved, but package size increases and signal delay occurs
Solution Approach 1:
The patent extracts the bonding wire from the system by implementing direct contact between chip terminals. The terminal structure includes a contact pad on the first chip and a contact protrusion on the second chip that directly touch without requiring external bonding wires, thereby eliminating the space occupation and signal delay issues associated with wire bonding
Solution Approach 2:
The patent transitions from planar wire bonding to vertical direct contact by designing terminals that extend toward each other in the thickness direction. The contact pad and contact protrusion are positioned to face each other across the bonding interface, enabling electrical connection through vertical alignment rather than lateral wire routing
2Reliability
If wire bonding technology is used to couple stacked semiconductor chips, then electrical connections between chips are achieved, but fabrication complexity increases
Solution Approach 1:
The patent merges the terminal formation process with the chip fabrication process itself. The contact pad and contact protrusion are formed as integral parts of the chip structures through standard semiconductor manufacturing steps (pattern formation, electrode deposition), eliminating the need for separate wire bonding fabrication steps and reducing overall process complexity
3Ease of manufacture
If terminals are exposed for wire bonding, then wire bonding coupling is enabled, but chip size must be increased
Solution Approach 1:
Instead of exposing terminals on the chip surface for wire bonding to approach from the side, the patent inverts the approach by having terminals extend toward each other in the thickness direction. The contact pad and contact protrusion are positioned to face each other vertically, enabling connection without requiring lateral space for wire bonding access
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. A semiconductor chip included in the semiconductor device includes a pillar-shaped terminal and a pad-shaped terminal in a terminal region. The pillar-shaped terminal is exposed at a first surface of a chip substrate in the terminal region and the pad-shaped terminal is exposed at a second surface of the chip substrate in the terminal region, where the first surface and the second surface of the chip substrate in the terminal region face oppositely from each other.