Pillar Transistor Gate-Through Structure for Denser DRAM Arrays
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Solution Overview
Problem
Current DRAM architectures face challenges in achieving high levels of integration and packing density due to limitations in the configuration of wordlines within memory arrays, which restricts scalability and fabrication complexity.
Innovation Solution
The integration of transistors with conductive gate material passing through pillars of semiconductor material, allowing for wider spacing between wordlines and simplified connections, enabling more efficient and scalable memory array configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional DRAM architectures are used with traditional wordline configurations, then fabrication processes are simplified, but packing density and integration level are limited
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional stacked architecture. Memory tiers are stacked vertically with through-silicon vias (TSVs) enabling inter-tier connections. Wordlines extend through multiple tiers vertically, and bitlines connect horizontally across tiers, creating a 3D memory structure that dramatically increases packing density while maintaining fabrication feasibility through standardized stacking processes
2Quantity of substance
If wordlines are closely spaced to increase integration, then packing density improves, but fabrication precision requirements increase
Solution Approach 1:
By moving to 3D stacked architecture, the patent achieves higher integration levels through vertical stacking rather than horizontal packing. The TSV technology enables precise vertical alignment between tiers, and wordlines are formed through conformal deposition processes that ensure uniform spacing. This dimensional transition allows high integration without requiring extremely tight lateral spacing, thereby reducing manufacturing precision requirements compared to planar scaling
Solution Approach 2:
The memory array is segmented into multiple discrete tiers stacked vertically, with each tier containing a subset of memory cells. This segmentation allows independent formation and testing of each tier, and enables parallel processing during fabrication. The modular tier structure reduces the precision burden on any single wordline formation step while achieving high overall integration through the cumulative effect of multiple tiers
Data Source
AI summary
Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the segments, and a channel region is within the segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions. Some embodiments include methods of forming integrated assemblies.