Pillar Semiconductor Transistor Layout for Isolated N+ Epitaxy
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Solution Overview
Problem
The challenge in further reducing chip size for high-density semiconductor devices, such as SRAM cells, is the need to form pillar-shaped semiconductor transistors (SGTs) without contact between adjacent N+ layers, which requires precise control over the formation of impurity regions and gate conductor layers to maintain high integration and performance.
Innovation Solution
A manufacturing method involving selective epitaxial crystal growth and precise etching techniques to form SGTs with optimized spacing and crystallinity, ensuring that impurity regions and gate conductor layers are separated and connected effectively, allowing for high-density SRAM cell formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective epitaxial crystal growth method is used to form N+ layer on top of Si pillar, then resistance of N+ layer is reduced, but N+ layer expands outside periphery of Si pillar causing contact between adjacent structures
Solution Approach 1:
An insulating layer is introduced as an intermediary between adjacent Si pillars. This insulating layer prevents lateral expansion of the N+ layer from contacting adjacent structures, thereby maintaining low resistance while preventing unwanted contact between neighboring pillars
Solution Approach 2:
The insulating layer is formed on the gate insulating layer and gate conductor layer before forming the N+ layer. This preliminary action creates a controlled boundary that guides the epitaxial growth of the N+ layer, ensuring it remains confined and prevents lateral expansion issues
2Quantity of substance
If chip size is reduced for high integration, then density of semiconductor device is increased, but precise control over impurity regions and gate conductor layers becomes more difficult
Solution Approach 1:
The structure is segmented into distinct functional layers: gate insulating layer, gate conductor layer, insulating layer, and N+ layer. This segmentation allows each layer to be formed and controlled independently, maintaining manufacturing precision even as device density increases
Solution Approach 2:
Different regions are assigned different properties: the gate insulating layer and gate conductor layer provide electrical control, while the insulating layer provides physical separation. This local differentiation enables precise control over impurity regions and gate conductor layers in high-density configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of high-density SRAM cells with improved crystallinity and reduced resistance, achieving the goal of high integration and performance in semiconductor devices.
Implementation Method 1
An N+ layer is formed on top of the Si pillar by a semiconductor layer such as Si, SiGe containing single crystal donor impurities by selective epitaxial crystal growth method
Data Source
AI summary
A gate TiN layer of adjacent Si pillars among Si pillars contacts at entire channel length in a vertical direction. SiO2 layers are formed, surrounding the Si pillars, and mask material layers on top thereof, and being spaced from each other. Then, a SiN layer is formed surrounding the SiO2 layers. Then, the mask material layers and the SiO2 layers are removed. Then, a P+ layer and N+ layers which upper surfaces are lower than an upper surface position of the SiN layer are formed surrounding each top of the Si pillars by selective epitaxial crystal growth method.